<rant>
Sure is also easy to tell the guys who *work* in semiconductor process design and manufacturing and understand these issues from those that don't.
Tell me, how would a motherboard BIOS issue create a flakey indivual core problem?
</rant>
It certainly can be a mask+process issue. The thing of it is that, even with a defect, it might not appear the same on every wafer. Believe it or not, the biggest issue facing those CPU manufacturers is variability. And the variability between lots, wafers, and even withing a wafer itself can be quite large. I'm more familiar with variabilty that can come from the patterning process (scanner dose, defocus, topography ("flatness" of the underlying features), scanner hotspots, temperature control, developer puddle, random etch residuals....)
Especially when given a portion of a design which is particularly prone to failure under process variability.
And it's not true that, just because you don't see it in the Athlons doesn't mean it's not a overall process problem. Certain design layout geometries are particulary poorly suited to handle the variabilities. No single design will explore all possible design space. AMD is at a particular disadvantage here becuase of the larger disconnect between design and process development.
I am leaning toward, not the design itself, but what it on the reticle itself that's the problem -- assuming the reports of the problem being dominant in core #2. And assuming the design itself is symmetrical. You see, even though the design of the four cores might be the same, it is NOT a guarantee that the data on the reticle will be. There are a number of data processing steps while taping out the reticle which subtly alter the design, and if the error is in there.
but hey, what do I know. I don't work for AMD and I don't know the details of the issue.