Presscoot official information and also the true

[juin]

Go anandtech.com all info

16 KB L1 data

Just next to the lab and the bunker you will find the marketing departement.

 

[juin]

??????????

Intel say

less lantency on integer multiplie mean less cycle

Just next to the lab and the bunker you will find the marketing departement.

 

[Quetzacoatl]

don't they mean less latency altogether?

Instead of Rdram, why not just merge 4 Sdram channels...

 

[juin]

all instruction have a lantency time or number of stage look like Integer multiplier will be faster as having less stage maybe 5 to 4 or something like that or i just get too excited wich can be more logic.


The complete list of improvement on Prescott

New clock distrubution """almost"" kill all skew in the chip where northwood was facing 1 of this issue

a New 16KB data cache i guess it all also run at the same lantency

13 new instruction some may have allready hear about Monitor

Improve pre-fetch

800 FSB 1MB of L2 cache how about the lantency i guess we would have to wait to release of the chip.

La grande will be support
Advanced power mmanage i guess this can help for overall sound and power consumation.

Also the New improve ALU to wich extend we will have to wait or intel will be more specifque later at the IDF

Just next to the lab and the bunker you will find the marketing departement.