Reading Comprehension - Memory

[shaharhada]

Double data rate (DDR) memory controllers are used to drive DDR SDRAM, where data is transferred on both rising and falling edges of the system's memory clock
What the meaning of rising and falling edges [of the system's memory clock)?
From the source:
https://en.wikipedia.org/wiki/Memory_controller

 

[kanewolf]

Double data rate (DDR) memory controllers are used to drive DDR SDRAM, where data is transferred on both rising and falling edges of the system's memory clock
What the meaning of rising and falling edges [of the system's memory clock)?
From the source:
https://en.wikipedia.org/wiki/Memory_controller

The waveform for the clock signal is a square wave -- https://en.wikipedia.org/wiki/Square_wave#/media/File:Waveforms.svg
The memory can transfer data when the voltage transitions from low to high AND from high to low. Those two transitions are referred to as the rising edge and falling edge of the waveform.

 

[shaharhada]

Thanks.

Thanks.
In the same source:
What is agnostic memory control design?
What is agnostic?
"In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing the memory cell agnostic memory control design, but this had not been demonstrated, as the technology is in its infancy."

 

[kanewolf]

Thanks.
In the same source:
What is agnostic memory control design?
What is agnostic?
"In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing the memory cell agnostic memory control design, but this had not been demonstrated, as the technology is in its infancy."

Agnostic means not specifically designed or tailored for something. A person is a pizza agnostic if they don't care if they eat pizza or don't eat pizza, for example.
In your above quote, the author is saying the the FB-DIMM (fully buffered memory) buffer could be designed to HIDE the specific design of the DRAM behind the buffer. That would allow the design to use any kind of memory architecture ever designed. The memory controller would be agnostic (doesn't care) about the hardware behind the buffer.