News Rumor: Next-Generation Intel Core i7 To Feature 8 Cores With 12-Core Hyperthreading

[Admin]

Queuing the salt truck on this one

Rumor: Next-Generation Intel Core i7 To Feature 8 Cores With 12-Core Hyperthreading : Read more

 

[InvalidError]

Well, if Intel is going big.LITTLE, it wouldn't be surprising if the big cores were full-blown ones with SMT and the little ones were Atom-like without it to save space and power.

 

[nofanneeded]

Intel would no longer be able to cram 10 cores onto the die as it would grow too big, as even the Core i9 10900K is already at the limits of what the 14nm silicon can do

really ? last time I checked 14nm can do alot , intel already has 18 cores HEDT CPU using that process...

it is not a limit , it is just marketing . and please dont bring on the socket size , because,

one : this is just your guessing and nothing official from intel papers.

and two : you are not a CPU designer you are just a writer .

thanks , waiting for more "tomshardware going down" articles

 

[InvalidError]

it is not a limit , it is just marketing . and please dont bring on the socket size , because, one : this is just your guessing and nothing official from intel papers.

Well, the die has something like a 2.5:1 aspect ratio, so there certainly is more than enough room to make the die twice as wide under the square IHS. Power delivery for such a doubled-up monstrosity on the other hand could definitely be an issue and require a few hundred more Vcore+ground pins. Most of the extra pins on LGA1200 are for PCIe 4.0 support and to implement the 4.0x4 NVMe interface, not much extra power to be had there.

 

[spongiemaster]

really ? last time I checked 14nm can do alot , intel already has 18 cores HEDT CPU using that process...

HEDT CPU's don't have an IGP like desktop chips do.

 

[Chung Leong]

Well, if Intel is going big.LITTLE, it wouldn't be surprising if the big cores were full-blown ones with SMT and the little ones were Atom-like without it to save space and power.

The other way around seems more sensible. Pipeline stalls are more likely to occur in the small cores due to smaller caches and weaker branch prediction. Disabling SMT in the big cores could meanwhile allow for higher boost frequency.

 

[Deicidium369]

Well, if Intel is going big.LITTLE, it wouldn't be surprising if the big cores were full-blown ones with SMT and the little ones were Atom-like without it to save space and power.

Alder Lake will be the Big Little thing - the 8C 12T is for Rocket Lake and is a typo in the leaked photos

 

[Deicidium369]

really ? last time I checked 14nm can do alot , intel already has 18 cores HEDT CPU using that process...

it is not a limit , it is just marketing . and please dont bring on the socket size , because,

one : this is just your guessing and nothing official from intel papers.

and two : you are not a CPU designer you are just a writer .

thanks , waiting for more "tomshardware going down" articles

Intel has 28C 14nm CPUs...

 

[Deicidium369]

Queuing the salt truck on this one

Rumor: Next-Generation Intel Core i7 To Feature 8 Cores With 12-Core Hyperthreading : Read more

Most likely a typo

 

[InvalidError]

The other way around seems more sensible. Pipeline stalls are more likely to occur in the small cores due to smaller caches and weaker branch prediction. Disabling SMT in the big cores could meanwhile allow for higher boost frequency.

While SMT on low-power cores may be ideal for highest efficiency, SMT on the fast cores is ideal for peak throughput. It is extremely unlikely that the minimal boost gains (at stupid power cost) you might get from removing SMT would offset the 30-40% throughput loss. And at only ~5% silicon and power cost, SMT is far more power- and silicon- efficient than high-efficiency cores too.

 

[1_rick]

Well, if Intel is going big.LITTLE, it wouldn't be surprising if the big cores were full-blown ones with SMT and the little ones were Atom-like without it to save space and power.

Surely if they were going to do that there'd be mention of it. And it also raises--not begs--the question of why only the i7 would be big.LITTLE.

 

[1_rick]

HEDT CPU's don't have an IGP like desktop chips do.

Still, compare the size & shape of the 18-core HEDT dies to even the 10-core Comet Lake. Lots of room to expand horizontally.

 

[InvalidError]

Surely if they were going to do that there'd be mention of it. And it also raises--not begs--the question of why only the i7 would be big.LITTLE.

Well, it was apparently a typo in this case. Alder Lake is where the big.LITTLE party is starting.

 

[Chung Leong]

While SMT on low-power cores may be ideal for highest efficiency, SMT on the fast cores is ideal for peak throughput. It is extremely unlikely that the minimal boost gains (at stupid power cost) you might get from removing SMT would offset the 30-40% throughput loss. And at only ~5% silicon and power cost, SMT is far more power- and silicon- efficient than high-efficiency cores too.

Scaling beyond four threads is generally not very good. I'm not convinced that 8 virtual cores would beat 4 physical cores in computational intensive tasks. Using SMT on the smaller cores makes more sense, as the very fact that a thread gets assigned to them means it's not demanding performance-wise. Latency might matter more and you get more finely divided time slices from SMT than from the OS.

Of course, it could simply be a typo

 

[InvalidError]

I'm not convinced that 8 virtual cores would beat 4 physical cores in computational intensive tasks.

If the contest is between full-blown Ice Lake cores with SMT to feed its 10-wide execution back-end and twice as many non-SMT Atom cores with only three execution units, I think it is a pretty safe bet Atom will get its ass served to itself on a silver platter.

 

[spongiemaster]

Still, compare the size & shape of the 18-core HEDT dies to even the 10-core Comet Lake. Lots of room to expand horizontally.

Rocket Lake isn't using Skylake cores. We're not sure exactly what it is using, but even if they only move to Sunny Cove, it will have 38% more transistors than Sky Lake. Increase transistor count by at least 38% per core and add an IGP, and the 18 core HEDT becomes irrelevant as a measuring stick.

 

[chalabam]

8 Cores after 2020?

Pathetic.

This is why Nvidia is worth more than Intel.

 

[Deicidium369]

8 Cores after 2020?

Pathetic.

This is why Nvidia is worth more than Intel.

LOL - You really don't know how the stock market works, do you? Nvidia has a 78x p/e ratio (undoubtedly due to the Ampere and Ampere GeForce launches) and Intel has a 10.92x. So, yes with that high P/E Nvidia has a higher market cap that Intel ATM. Q22020 Revenues at Intel are $18.5B - which is almost 2x the revenue for Nvidia for an entire year.

$1.00 earned at Nvidia is worth $78.00 in market cap. $1.00 earned at Intel is worth $10.92 in market cap - simplistic but illustrative.

P/E imbalances also allow things like Tesla (trailing p/e 214x) being worth more the Toyota (9.31x)... Tesla is amazing - great cars - but only sell a tiny fraction of Toyota sales.

People are too caught up in the moar coarz game - The July benchmarks for Tiger Lake (4c) vs 4800U (8c) shows that in CPU (GPU in the TGL destroys the 4800U and matches the MX350) that AMD's 8 core only out performs the 4 cores in the TGL by 17 or 18% - despite 2x the cores. Xe LP (the 96EU iGPU in Tiger Lake) already slightly edging out MX350 - not bad for a 1.0 product.

"Summing up the performance metrics, the Intel Core i7-1165G7 has a lead of up to 20% in single-core performance tests while featuring a 10% clock speed advantage over the Ryzen 7 4800U (4.2 GHz vs 4.7 GHz). In multi-core tests, the Ryzen 7 4800U is 17% faster but that is despite the AMD chip having twice the number of cores and threads. But that's the fastest score for the chip with Linux OS which tends to offer higher scores. Compared to a Ryzen 7 4800U on Windows OS, the Core i7-1165G7 leads by up to 35% in single-core while being just 6% slower than its 8 core & 16 thread competitor. "
https://wccftech.com/intel-10nm-cor...vs-amd-7nm-ryzen-4000-upto-20-percent-faster/

Sunny Cove brought significant IPC increases, as does Willow Cove in the TGL. So while AMD is shouting moar coarz, and having that advantage kneecapped by an actual new micro arch and no longer just a retread of Skylake (where AMD is aiming) - it's all moot. Ice Lake SP will outsell Epyc at least 10:1 - that 95+% data center market share is mostly 2 socket servers.

So while Intel is pretty boring at less than 11x - with Ice Lake SP Xeon, Tiger Lake and later with Rocket Lake and Xe Discrete Graphics cards releasing this year- Nvidia's momentary market cap advantage will be negated. Revenue matters.

 

[Chung Leong]

If the contest is between full-blown Ice Lake cores with SMT to feed its 10-wide execution back-end and twice as many non-SMT Atom cores with only three execution units, I think it is a pretty safe bet Atom will get its ass served to itself on a silver platter.

If you win a contest and nobody notices, did you really win a contest? The whole idea behind a hybrid architecture is that oftentimes finishing a task quicker is not worth the energy cost. The small cores are supposed to handle most of the work. The big cores are to be used where performance matters (from the end user's perspective). SMT in the big cores doesn't make sense since we're not trying to maximize utilization of that hardware.

 

[InvalidError]

If you win a contest and nobody notices, did you really win a contest? The whole idea behind a hybrid architecture is that oftentimes finishing a task quicker is not worth the energy cost.

Most desktop applications are bound by single-threaded performance - finishing individual critical tasks as fast as possible and the cheapest way of giving more things a chance of completing as fast as possible is SMT on very fast cores.

 

[PCWarrior]

Rocket Lake isn't using Skylake cores. We're not sure exactly what it is using, but even if they only move to Sunny Cove, it will have 38% more transistors than Sky Lake. Increase transistor count by at least 38% per core and add an IGP, and the 18 core HEDT becomes irrelevant as a measuring stick.

Sunny Cove has 18% higher IPC on average than Skylake. Willow cove will have at least 10% IPC improvement on top of that so Willow Cove should have around 30% higher IPC on average compared to Skylake. On pure-throughput applications such as tile-based rendering the increase will be closer to 40%. That should correlate with the increase in transistor count. So, per core, Willow cove full-blown cores should feature around 40% more transistors than Skylake-S cores. So 10 cores of Rocketlake-S should roughly take the same die area as 14 Skylake S cores. A Skylake i-gpu, in terms of die area is the same as 2 Skylake S cores. The Tigerlake igpu will probably be the same size as 4 Skylake cores. So a 10-core Rocketlake-S CPU will roughly take a total area equivalent to 18 Skylake S cores (14 Skylake cores for core logic + 4 Skylake S cores for the igpu). PCIe 4 will at worst take as much area as twice the PCIe3 lanes – so for 16PCIe4 lanes+8PCIe3 lanes will take the same area as 40PCIe3 lanes.

Intel can produce 18-core HEDT cpus with 18 Skylake X cores (which are even larger than Skylake S cores as they also feature AXV-512 – though Willow cove cpus will feature AVX-512 too), a quad channel memory controller and 52(=48+4) PCIe3 lanes. So Intel can perfectly produce a 10-core Rocket-lake with Xe igpu, dual channel ram, 16 direct PCie4 lanes and 8PCIe3 DMI 3.0 link to the chipset.

What is more is that there have been rumours that Intel will opt to decouple the igpu from the cpu die like they did with Clarkdale 10 years ago. As with Clarkdale they will make the two dies on two separate nodes (back then they used 45nm for the igpu and 32nm for the cpu die) but unlike Clarkdale it will be the igpu die that will get manufactured on the newer node this time. This will allow Intel to do two things: (i) Market this as a hybrid 10nm/14nm product and (ii) fit even more transistors on the cpu die for either more cores or more logic/cache per core if they want to. They can certainly put 12 full-blown cores this way and still occupy less die area than a 10980XE.

Also let’s not forget that AMD with TSMC’s 7nm (equivalent to Intel’s 10nm) uses more die area for core logic than Intel does on 14nm, while also failing to feature an igpu and while all the I/O and the memory controller is located on a separate die. So much about the density superiority of the 7nm node… Anyone who has worked with FPGAs and ASICs knows very well the die-area savings of custom made silicon vs using a ‘sea of gates’. Similarly, Intel’s tailor-made cpus utilise the last ounce of the die – take a die shot of an Intel cpu and you can clearly identify cores, cache slices, etc as if it is a perfect block diagram. You can’t say the same for AMD cpus build on a generic process where while you can still identify the cores you can clearly notice how sparser things are.

 

[1_rick]

Rocket Lake isn't using Skylake cores. We're not sure exactly what it is using, but even if they only move to Sunny Cove, it will have 38% more transistors than Sky Lake. Increase transistor count by at least 38% per core and add an IGP, and the 18 core HEDT becomes irrelevant as a measuring stick.

Sure, but look at various chip pictures, and physical sizes. I'm just saying I bet it's possible.

 

[spongiemaster]

Sure, but look at various chip pictures, and physical sizes. I'm just saying I bet it's possible.

10 cores appears to be about the limit for a single ring bus. With the mesh architecture that HEDT uses, Intel can have more than 2 "rows" of cores which isn't possible with the ring bus, unless they utilize a dual ring bus which they haven't used in years and wouldn't on a mainstream consumer CPU. There is a reason that mainstream CPU's are rectangular. They can't just fill in the square. We don't know what affect these larger cores will have on clock speeds and power, but we can assume it won't be positive. So, just because it could be physically possible to squeeze in more cores, there are many factors that contribute to whether or not it would actually work as a product. Intel probably felt safer scaling this back to 8 cores from the 10 that the 10900k has. 9900k die below.

 

[InvalidError]

There is a reason that mainstream CPU's are rectangular. They can't just fill in the square.

If Intel really wanted to, I'm sure it could make the die square-er by re-arranging the IGP such as moving the IGP to the bottom edge and integrating its ring agent into the system agent (effectively giving the IGP its own single-stop ring) instead of dangling off the CPU ring.