SOI

[endyen]

IBM gets a lot of the credit. The R&D guys are paid by a consortium that is paid by Sony, Hitachi, AMD, NEC, Infineon, Samsung, Chartered, and IBM. Not all players are in for all the projects, but immersion includes most of them.

 

[JAYDEEJOHN]

Isnt the bulk of the work being done in IBM labs? by the consortium?

 

[endyen]

Some is done at East Fishkill, some at Dresden. Most is done at universities around the world.

 

[apache_lives]

It makes Intel a failure coz they couldn't do it

Try comparing an Intel Dothan to an AMD 90nm based part with SOI - see who comes out on top in performance and power consumption

 

[Reynod]

endyen ... thanks for the article.

Pentium M was a big step for Intel ...

I wonder ... was it a bigger step in terms of IPC from P4 to M than M to Core2?

Assuming the same clock speed that is?

 

[apache_lives]

endyen ... thanks for the article.

Pentium M was a big step for Intel ...

I wonder ... was it a bigger step in terms of IPC from P4 to M than M to Core2?

Assuming the same clock speed that is?

The Pentium M was based off the pentium 3, a few minor adjustements, more cache, QDR FSB.

Intels been working on the P6 design for years and with every generation it reduces power/heat while steadily improving clocks and performance (IPC) - Pentium Pro - Pentium II - Pentium III - Pentium M - Core Duo - Core 2 Duo, each step brings additional performance and power savings/efficency, as for the leap between the Pentium 4/D and the Core 2 Duo, well overdue there so expected, but the jump from Yonah to Meron (Core Duo to Core2 Duo) wasnt that great, apart from being moved back to the desktop as Conroe.

 

[sonoran]

You may have seen a comleted wafer. You may have noticed that while the transistors cover the whole wafer, many on the outside look like they are not complete chips.
Just a few examples of where celerons come from.

Actually, those wafers you always see with partial chips on the outside edges are test wafers. The fab guys would know better than me, but for production use, I believe they optimize the litho process so it doesn't even image those parts of the wafer. (The litho tools don't image the entire wafer in one shot - they image a few chips then step over to do the next few.) Litho tools are the most expensive in a fab (and getting much worse with every new generation). You can bet they strive to use them as efficiently as possible.

 

[endyen]

Actually, those wafers you always see with partial chips on the outside edges are test wafers. The fab guys would know better than me, but for production use, I believe they optimize the litho process so it doesn't even image those parts of the wafer. (The litho tools don't image the entire wafer in one shot - they image a few chips then step over to do the next few.) Litho tools are the most expensive in a fab (and getting much worse with every new generation). You can bet they strive to use them as efficiently as possible.

Too true, but remember those wafers cost $300 to over $1000 a pop. They make every effort to get the max from each one. It is also a question of max output. You only have a limited # of Wafer Starts Per Month. AMD only has Dresden, while Intel relies heavily on D1D when they first start a new node, or any other major change.