A question I have about the substantial amount of PCIe lanes is... Are they all 3.0? Or is it 16 3.0 lanes and 48 2.0 lanes? There's no specific mention of all the PCIe lanes being 3.0?
AMD used the same Zeppelin die for Ryzen, TR and EPYC. EPYC has 128x PCIe 3.0 even in 1S configuration, which means that each Zeppelin die has at least 32x PCIe 3.0.
The power and die area cost of PCIe 2.0 and 3.0 is practically the same, it wouldn't make much sense to mix them and that's why you only see CPUs implementing one type. Chipsets don't have sufficient upstream bandwidth to support PCIe 3.0 on their downstream ports and that's why most chipsets still only support PCIe 2.0 on their ports.
The most interesting discrepancy between EPYC and the other CPUs is that EPYC has no chipset. Instead, some of its PCIe lanes can also be used for USB3 and SATA3. I call that interesting as it means that AMD's whole lineup could have been designed to be chipset-less. Guess we'll get there on AM5 in 3-4 years.