I highly doubt intel is using chiplets. What they usually do is to combine 2 dies to double the core count
In the end this doesn't matter. It is a MCM design one way or the other.
Additionally this would give them the opportunity to double memory channels (and probably also PCIe lanes), if they intend to (?), as they have already done with Cascade Lake AP with 12 memory channels.
Finally it is very likely, that this design (if it's no fake) will simply be an extension to their expertise with Cascade Lake AP.
The main question is: How efficient will be their third process iteration 10nm+++ aka
Enhanced SuperFin because this will limit core scaling in the end. The design will be released after Milan and most likely outperform it (in special workloads even by far), but it will be released shortly before Genoa in 5nm, which puts it in a difficult position (
because originally Granite Rapids SP in 7nm should have been the competitor for Genoa, but with the 7nm delay, this server will arrive not until the first half of 2023).
Yes, this.
I bet each of those 'chiplets' is about twice as large as an entire Ryzen CPU. This is probably more like the Pentium D 2021 edition. 😉
Of course it will be larger. Already Ice Lake SP will provide 32 to 36 (?) cores on a monolithic die, therefore of course it is significantly larger than a
Ryzen CPU with only up to 16 cores.
🙄
Btw: 3900/50X and 5900/50X require ~ 273 mm2 die area.
Skylake SP (in 14nm) as HCC with up to 18 cores has about ~ 428 mm2, therefore you can estimate that an HCC for Ice Lake SP or Sapphire Rapids SP will be significantly smaller and therefore still larger but far away from doubling the area (compared to a Ryzen).
But if you had something different in mind, a 64 core Rome/Milan/Threadripper has a die area of about ~ 1008 mm2. This also means, that a 64 core Sapphire Rapids SP most likely *) will only require a few square millimeters more (if at all) than Milan, because Intel produces these die(s) completely in 10nm whereas AMD still uses a very large 14nm IO-die (
the IO-die for Ryzen's is produced in 12nm, the one for Rome in 14nm; currently it is unclear if AMD had possibly shrinked it to 12nm for Milan).
A 32 core Epyc/Threadripper currently requires at least ~ 712 mm2 with four chiplets, therefore it is safe to assume, that a 32 core Intel die will require less area. Already a 28 core Skylake SP in 14nm only requires 602 mm2.
*) "Most likely" because it also depends on the amount of increased caches and possibly "much broader" cores.
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