>But did you find that date yet in the table that showed a
>worse scenario than today?
How hard can it be ? Oh well, here you go:
Q2 1997
Pentium II 233: $637
Pentium II 266: $775
Pentium II 300: $1981
I'm sure that proved the end of innovation and the semi industry hitting a brick wall
> I think it's a bit naïve to assume that if a CPU
>technology has continued to grow steadily for the past
>fifteen years, it will grow forever.
I would use "shrink" instead of "grow" in this context
😛
Anway, its not 15 years its roughly half a century. And during all this time, each year the end was near according to some. You did read that Amdahl's quote of mine, didnt you ? Well, since I am no Jehova witness, so I'll just see it when it happpens. Not any time soon though.
>Name one application that would never run faster on
>multiple processors.
Duke Nukem Forever ?
Leasure Suit Larry II ?
Heck, even "Quake 3 -r_smp 1"
Now can you name me one application that will never benefit from faster clocks, or higher single threaded IPC ?
> AMD's less radical approach shows that this is not the
>only way to increase performance. IPC matters, and soon
>they'll realize TLP matters as well.
"soon" ? LOL, K8 was designed from the ground up to support multicore, and I learned of their 2 way core plans over 6 years ago. P4 was supposed to (and may still for Xeon )go multicore, as IPF obviously, but 2 way CMT dothans are a contingency plan that has not started longer than a year ago at most and I assure you the venerable Pentium Pro core did not have provisions for it.
> I'm currently working on a camera surveillance system
>where several cameras are shown on one monitor, using
>motion detection to pick the most interesting ones to
>display. It's really 'natural' to use a thead per network
>connection
OF course it is. Now consider how you'd speed up the motion detection algorithm of just ONE camera using multi threading... Tell me it is as easy as implementing MMX or SSE.
> Katmai has 9.5 million transistors, Prescott has 125
>million (75 excluding the cache)
Katmai had 0 Kb level 2 cache. You should count at least the off die cache chips as well, unless you really think even a dozen Celeron 300 (not A) cores bundled in one chip would be faster at ANYTHING as a 3+ GHz Prescott.
Even more fair, compare a .13 512 Kb P3 tualatin to a .13 512kb northwood. 44M for tualatin, 55M for Northwood (according to sandpile). How do you think a 1.4 GHz tualatin faires against a 3 GHz northwood ? Both using the same process, same cache size, comparable transistor count.
>And these phantom transistors are going to do what, double
>performance?
My guess is those phantom transistos are there for some form of DMT, which might indeed double performance in some cases (if it worked, and wouldnt send power consumption through the roof). Just like dual core might (nearly) double them in some. But like I said, try and ignore Prescott, its a wreck as it is, we know that.
>40% of Prescott transistors (cache) is on 30% of its die
>space. This tells me cache fits on 75% of logic space. Well
>if that's your definition of "MUCH more dense" then I can
>still fit in nearly a dozen Katmai cores.
Prescott uses 23 mm^2 for its 1 MB L2 out of 109 mm², so 21%. If that indeed consitutes 40% of its transistor count (I don't have a reference here, go a link ?), it means its ~2.5x as dense, MUCH denser indeed. i think you got your math wrong here:
Density= transistor count/mm²
prescott is 125M transistors
cache density = 40%x125M/23mm² or 2.2M/mm²
Core density = 60%x125M/86mm²=0.9M/mm²
If you divide the exact numbers the ratio is nearly spot on 2.5.
>Are you still sure that current single-processor technology
>is not in trouble?
Yes, I just think intel is in temporarely problems with their extreme speedracer design. The writing has been on the wall for a long time though.
= The views stated herein are my personal views, and not necessarily the views of my wife. =