AMD is in the mid-point of a unified memory architecture and controller for CPU cores and GPU shaders, operating as a *SIMD Engine Array* in GPGPU in co-operation with the integer CPU cores.
Interestingly enough, the ol' reliable 990X-FX series chipsets include IOMMU support which, given the potential of Steamroller cores and memory-controller/UNB integration in step 4 of the HSA arch, bodes well for AMD.
This being the case, I suspect they would like a little cooperation with the hardware vendors, too, in addition to co-operation from the OS and application software programmers would be nice.
To imply otherwise in the closing line of the article is simply flinging poo, uncalled for, and questions the objectivity of the author.
Also interesting is HSA with IOMMU, in combination with a quad-channel memory controller, and its pending integration with DDR4 ...
The DDR4 architecture is an 8n prefetch with two or four selectable bank groups. This design will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each unique bank group.... In addition, DDR4 has been designed in such a way that stacked memory devices... with stacks of up to 8 memory devices presenting only a single signal load.
Giggity. I see what they are trying to do. Each system device has recognized, mapped address space via the controller and UNB.