[citation][nom]rds1220[/nom]You missed the whole point of the article. You shouldn't need software to make a CPU great it should be great from the start. Yes Bulldozer had a lot of problems but Piledriver still isn't great, they still haven't compleatly fixed the IPC and the overall micro architecture still is slow and ineffcient compared to Intel. In single threaded programs the Piledriver still falls flat on it's face. Also I think you are giving Piledriver to much credit in heavily threaded programs. Yea it's better and it beats out the I7 in SOME programs but again the I7 is still faster and more effcient in most cases.[/citation]
Bullshit. AMD's greatest problems are their cache, not the micro-architecture. Also, please stop saying IPC because you don't seem to even know what it means. FYI, it's not performance per Hz. Furthermore, Piledriver isn't a less efficient architecture than anything from Intel. Compare the Sandy i5s to the Trinity A10s with their IGPs disabled and this becomes obvious where the A10s are actually more efficient. AMD's problems are mostly their crap cache and other front end issues, some of which, sure, are architectural, but that doesn't make it a bad architecture, it just means that it isn't perfect . Sandy/Ivy Bridge isn't perfect either and most certainly isn't superior, it's simply built with superior cache and process technology, something made obvious by the fact that they're architecturally very similar to Core 2 and Nehalem.
Also as proof of IPC not being what you seem to think it is, you should be aware of the fact that Bulldozer and Piledriver have exactly identical IPC despite not being the same micro-architecture and having different performance/power efficiency characteristics. Athlon II (AM3) and Phenom II (AM3) also have exactly identical IPC and have exactly identical micro-architectures too, but their different caches (Phenom II, excluding the 840 and 850, having an L3 cache of varying capacity but usually 6MiB and Athlon II not having an L3 cache as well as having varying L2 cache per core between different SKUs) gives them different performance.