76.8GB/s of memory bandwidth in 2004

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charliec2uk

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But surely it is more sensitive to noise as the switching thresholds get closer together...

By the way, I think there is a finite speed that one could scale a microprocessor. 1/Planck unit of time. Just a random thought but theorically that is faster frequency possible, but its a damn big number.

Democracy Bernad, it must be stopped!
 

Raystonn

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"surely it is more sensitive to noise as the switching thresholds get closer together"

This is why you need more precise technology. This technology is required on both the sending and receiving ends of the bus to reduce the noise.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

LoveGuRu

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ray, if you got a program compiled in 32 bit mode wouldnt you need to add another 32bit to it so you could preocess it?
or is it the partition that has to be 64 bit?

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Raystonn

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ray, if you got a program compiled in 32 bit mode wouldnt you need to add another 32bit to it so you could preocess it?
or is it the partition that has to be 64 bit?
I have no idea what you are talking about...

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

LoveGuRu

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you cant just send a 32 bit chunk into your processor, on of the steps would have to add another 32 bit for it to go in

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Boondock_Saint

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Software is either compiled or done on the fly to go through 64 bit type systems, I believe. You do not just "add" extra bits; it's the way the code is divided.

:tongue: Have you ever tried cooking an egg on your HSF? Tasty. :tongue:
 

bum_jcrules

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Sorry had to drive home and eat dinner...

Pannel -

What happens if you open up the bus for SDRAM/DDR? Higher latency?

Secondary question:

If RDRAM is serial, the more RIMMs you have the higher the latency. This is right...Right? The signal would have to pass through each RIMM and then back. (Strobe that is)

<b>Egon, Remember that time you tried to drill a hole through your head? - Ghostbusters</b> :lol: <P ID="edit"><FONT SIZE=-1><EM>Edited by Bum_JCRules on 10/23/01 08:07 PM.</EM></FONT></P>
 

lhgpoobaa

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no ncogneto... i was NOT refering to you with the troll comment.
it was aimed squarely towards Mr intel_inside_brain_absent.

one can hold any conviction, and i will respect that, provided of course one can display maturity.


Religious wars are 2 groups of people fighting over who has the best imaginary friend.
 

bum_jcrules

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Since RDRAM is in series...power fluctuations are more dangerous that a parallel setup.

What about power consumption of RDRAM. Won't that cause a problem? I know that Yellowstone is going to be a lower power solution but won't it still be a power-hog? With all of the banks turning on, well alternating banks, and dormant banks won't that cause a drain on the rest of the system. Not to mention fans, GPU, etc.?

<b>Egon, Remember that time you tried to drill a hole through your head? - Ghostbusters</b> :lol:
 

bum_jcrules

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Now that was the easy answer...

If RDRAM is to be the next form of RAM then it will have to be extremely low power for mobile systems.

I'll answer your response for you.

"Bet a bigger battery or two or three...or plug it into the wall."

But seriously, won't it still be a power-hog?

<b>Egon, Remember that time you tried to drill a hole through your head? - Ghostbusters</b> :lol:
 

bum_jcrules

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I just looked at Rambus' 1066 documentation...

What is the latency for a 512 stick of CAS 2-2-2 DDR?

RDRAM 1066 AKA Yellowstome will be 35ns.

But this of course is just on RIMM stick...and a few more.
Won't the latency in ns increase since it is in series?

Or because it is moving so fast it won't matter. But is should if the total time(ns) increases with more RIMMs.

<b>Egon, Remember that time you tried to drill a hole through your head? - Ghostbusters</b> :lol:
 

Raystonn

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you cant just send a 32 bit chunk into your processor, on of the steps would have to add another 32 bit for it to go in

The FSB on the Pentium 4 (and the Athlon as well) is 64 bits wide. Thus, the prefetcher/L1 must provide 64-bits of data at a time.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Raystonn

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Since RDRAM is in series...power fluctuations are more dangerous that a parallel setup.

What about power consumption of RDRAM. Won't that cause a problem? I know that Yellowstone is going to be a lower power solution but won't it still be a power-hog? With all of the banks turning on, well alternating banks, and dormant banks won't that cause a drain on the rest of the system. Not to mention fans, GPU, etc.?

Power consumption and quality are not issues at all any more than they are for SDRAM.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Raystonn

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Now that was the easy answer...

If RDRAM is to be the next form of RAM then it will have to be extremely low power for mobile systems.

I'll answer your response for you.

"Bet a bigger battery or two or three...or plug it into the wall."

But seriously, won't it still be a power-hog?

Unlike SDRAM, RDRAM has built-in power saving modes. It can be set to use less power than SDRAM.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

bum_jcrules

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I know what you mean now about Van Smith. I read his stuff over a year ago and I though since it was on THG it was gospel. He is so arrogant. He speculates way too much. It seems as if he analyzes before he gets his data results. Or should I say he hopes his data shows what he wants. (I know that sounds cruel but that is how it sounded today when I read it again. Each article seemed the same…Condescending.)

Thanks for not laughing at me too hard. :lol:


<b>Egon, Remember that time you tried to drill a hole through your head? - Ghostbusters</b> :lol:
 

bum_jcrules

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Ray-

I tried to find one of my old links to a website that had diagrams of the proposed DDR II but I can't find it.

I'll keep looking...

in the meantime here is the link to JEDEC.

<A HREF="http://www.ami2.com/shownews.asp?num=991" target="_new">http://www.ami2.com/shownews.asp?num=991</A>

<b>Did you see a little naked man running around with $100? - The Golden Child</b> :lol:
 

Ncogneto

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No, sorry, my apologies, however I do beleive your intial thread is pure speculation, and you have yet to convince me that a feasable motherboard could be built around the p4 platform that would even support this speculation.

You have taken a public announcement by RAMBUS of achieveing a Dram architecture ( in two years) that would support a bandwith of 3.2-6.4 gigs and expounded on that more than ten fold to 76.8 gigs. All of this in the same time frame. The problems with this, even if this was possible ( at least with the current p4) I have tried to illustrate. Honestly, I don't think you have come up with a workable solution in your proir examples. A 9.6 ghz fsb brings with it a multiple of problems which would need to be addressed in a relatively short time to be available by 2004. North bridges, south bridges, clock divisers for every component, let alone the EMT of such a high bus. I am just trying to fathom a north bridge capable of handling such a high clock rate. I don't think this was well thought out. Furthermore you later made claims of how this would effectively make video cards obsolete and this is so completely untrue also. Not unless the P4 has a programable T&L unit( among other) things in it which have yet to be activated?

I will give you this however, I do not see any Sdram derivative ever achieving such rates and if RDRAM can ( albeit I doubt by 2004) then DDR Ram has a very limited future. Problem is, even the makers of DDR Ram are not complete idiots, and if they could see such a ramping of RDRAM so quickly why do they even bother? So, 6.4 gig/s by 2004 maybe.....76.8 gig/s by 2004 I have my doubts. Like I said earlier, I believe the future will be in an entirely new memory different from both DDR/SDR or RDRAM coming on the scene at or around that time( 2004)( and this is speculation).

All that being said no I do not find you arrogant, but you have had occasion to jump the gun :)(But then again haven't we all?)

Video editing?? Ha, I don't even own a camera!
 

bum_jcrules

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Thinking of different memory types...

CRAM - Does anyone think that it could be a future path of RAM Architecture now that the processing/fabrication methods have improved as far as they have so far?

MRAM - Magnetic?? Hummmm... wouldn't magnetic fields cause interferance? Who am I to say? I work with money, Not an EE.

Hybrid memory types?

<b>Did you see a little naked man running around with $100? - The Golden Child</b> :lol:
 

Raystonn

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"You have taken a public announcement by RAMBUS of achieveing a Dram architecture ( in two years) that would support a bandwith of 3.2-6.4 gigs and expounded on that more than ten fold to 76.8 gigs."

With a dual 64-bit PC1200 RDRAM channels you clearly have 19.2GB/s of bandwidth. This technology was already on Rambus's roadmaps for 2004 prior to their latest announcement. Their new announcement indicates that ODR technology will now be replacing the DDR technology within RDRAM by 2004. This speeds things up by a factor of 4. (Octal Data Rate is 4 times faster than Double Data Rate.) This brings us to PC4800 instead of PC1200 RDRAM. This allows for 76.8GB/s of memory bandwidth. Based on Rambus's latest announcement, I do not see how this figure is inaccurate.


"even if this was possible ( at least with the current p4)"

I never actually stated it would be available with the current Pentium 4 in 2004. You just assumed this. It will definately be available to companies that want it, but noone yet knows who that will be. I certainly hope Intel reaches for some of this bandwidth, but there are never any guarantees. The easiest route to take in 2004 would be to use a single 64-bit PC1200 RDRAM channel on a future motherboard. This would be a disappointment at only 9.6GB/s, but would still be well ahead of current-day bandwidth figures.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

bum_jcrules

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Thought...

Wouldn't these new bandwiths and pathways have to be build into new processor designs?

Current production vs. Intel's BBUL packaging ideas...

Humm??? Now current pathways to the chipset would have to be increased from the CPU...Yes?

Your thoughts...

<b>Did you see a little naked man running around with $100? - The Golden Child</b> :lol:
 

bum_jcrules

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As you can see by my selection of the happy face icon type of wink... I am not winking at you all...It is time for bed for me...I spent too much time on this forum last night waiting for replies on the memory page while all the while you were thalking about ODR RDRAM on the CPU page.(Make sense...NOT)

Anywho...Good Evening everyone...I need ZZZZZZZZZ's

I'll take your abuse in the morning. :smile:

<b>Did you see a little naked man running around with $100? - The Golden Child</b> :lol:
 

Ncogneto

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This allows for 76.8GB/s of memory bandwidth. Based on Rambus's latest announcement, I do not see how this figure is inaccurate.
Your math was never in question, only your timeline. If what you say is a given why didn't Rambus just announce what you posted?

Video editing?? Ha, I don't even own a camera!