juanrga :
hcl123 :
HTX breaks hUMA as much as NUMA.. traffic going Xbar to the IMC, would go Xbar+I/O link -> I/O link+Xbar to the IMC (integrated memory controller), being the I/O part kind of orthogonal, the real magic is at the links PHYs and cache controllers.
No. hUMA provides an Uniform Memory Access to procesors, NUMA provides Non-Uniform Memory Access to procesors.
Must have a lot of patience... this is child play... tricked by words LOL
Its hU-MA and NU-MA... the MA, "memory access", lets put it part. Then is *Heterogeneous Uniform* and *Non Uniform*. If it were only "uniform" as in "UNIFORM", it would had been just
UMA...
not hUMA.
The
NUMA you mention also provides an "uniform" view of system DRAM, in the sense you imply, specially the cache coherent extension.
Its an integral view of all DRAM attached, system memory, in an hierarchical view (from here the "N" of non comes).
And is kind of opposite of UMA ( not hUMA ), which has no hierarchical view, its a completely flat view of "physical memory", and so forcibly only one system memory pool.
Lets consider a 4 sockets AMD server system with 64GB for each socket. With NUMA each CPU inside each socket will see the total of 256GB of system DRAM in an hierarchical way, its kind of an evolution of SMP (symmetrical multiprocessing), only would need expensive software mechanisms to ensure coherency and consistency across nodes/domains... With ccNUMA each CPU inside each socket will see the total of 256GB of system DRAM in an hierarchical way, PLUS all the cache pertinently associated with coherency protocols, dispensing almost all software for consistency.
hUMA is the same, only replace the same "physical memory" with the "
same VIRTUAL MEMORY" (there is a difference if you didn't know), PLUS all the cache pertinently associated with coherency protocols ( as example in ARM the L1 is not coherent, its private, while in AMD L1 is coherent).
Actually ccNUMA is better and more straightforward for programming. The problem is that NOT ALL members of HSA use the same coherency schemes (as exposed), and AMD simply could not impose its coherency protocols on others, so something different " heterogeneous" had to be invented.
Actually i'm quite convinced that a hUMA prepared program could run unchanged on a ccNUMA system, that is, an AMD CPU + GPU in ccNUMA config... if that system TLBs and DMA understand the quirks of IOMMU, which in AMD i think they already do.
So its not "the opposite"...
its "very similar".
juanrga :
HT/HTX breaks hUMA, because the memory in the main bus would be faster than the memory accessed through the HTX slot.
But HT/HTX doesn't break hUMA, For that reason Hypertransport is used in NUMA architectures. AMD itself uses Hypertransport in a proprietary extension: ccNUMA.
So does "several processing elements" with several MMU/TLB, on a tightly integrated SoC. Several processing elements there must be arbitration/priorities, so faster and slower accesses. But if there is arbitration/priorities, this could very easily be made to deal with an I/O link in the middle, that is transparent for the processing elements operations.
The only "proprietary extension" on Hypertransport for this, is the MOESI coherency protocol that the HT PHYs must understand for ccNUMA with AMD CPUs. And since no other adopter of the Hypertransport.org does CPUs, remained subject to royalties... and will remain even if other IDM adopts HT and has its own coherency protocol adapted for those links PHYs. Then we will have 2 ccNUMA "proprietary extensions"... one for use with AMD CPUs, other to use with "other" CPUs.
There are more "royalty subjected proprietary" extensions on HT, besides this... HCN 2 (high count node), content aware routing... and more i think...
juanrga :
hcl123 :
So to be, to me was always identical to intel, a pool for CPU and a GDDR5 pool for the GPU, but "interposed in the socket subtract", like some mobile GPU parts of AMD have
No, it is one DDR3 pool or one GDDR5 pool, but not both at once. Kaveri comes with DDR3 support (hUMA), but there are rumours that a future high-end APU comes with GDDR5 pool, as in the PS4. As I said before a mixture of DDR3 and GDDR5 makes no sense because breaks hUMA.
The same mistakes out of the same lack of knowledge... but time over... you understand it now, or you never will, because simply you don't want to.
THIS ARE IMAGES OF 2011 AFDS (fusion summit),
http://www.google.com/search?q=AFDS+2011&num=20&as_qdr=all&tbm=isch&tbo=u&source=univ&sa=X&ei=6rUbUp-pGYH27Aaz0IAY&ved=0CLIBELAE&biw=1784&bih=817
then there aren't yet talks of cache coherency, but there were talks of... "UNIFIED MEMORY ADDRESSING" ... "MMU AND IOMMU"... and "
CLEAR SEPARATION OF GPU AND CPU, CPU WITH MMU, GPU WITH IOMMU"
http://www.google.com/imgres?q=AFDS+2011&sa=X&as_qdr=all&biw=1784&bih=817&tbm=isch&tbnid=ZGvfhnvtXNGd0M:&imgrefurl=http://adrenaline.uol.com.br/tecnologia/noticias/8878/arquitetura-com-coprocessador-escalar-sera-o-futuro-das-gpus-da-amd.html&docid=G1urLe9XA79dnM&imgurl=http://www.adrenaline.com.br/files/upload/noticias/2011/06/subzero/afds04.jpg&w=1035&h=609&ei=F7YbUqLLGYjQ7AbPxoDYAg&zoom=1&iact=rc&page=2&tbnh=172&tbnw=293&start=27&ndsp=29&ved=1t:429,r:39,s:0&tx=181&ty=82
ROADMAP up to "TOTAL SYSTEM INTEGRATION" (preemption/context)...
WITH CLEAR INDICATION OF > "EXTEND *TO* DISCRETE GPU "
http://www.google.com/imgres?q=AFDS+2011&sa=X&as_qdr=all&biw=1784&bih=817&tbm=isch&tbnid=9o25jFXVYmt5vM:&imgrefurl=http://semiaccurate.com/2011/06/20/amd-talks-about-next-generation-software-and-fusion/&docid=jnE1kIZbX7FjCM&imgurl=http://semiaccurate.com/assets/uploads/2011/06/AFDS_Rogers_FSA_map.jpg&w=600&h=277&ei=F7YbUqLLGYjQ7AbPxoDYAg&zoom=1&iact=rc&page=2&tbnh=152&tbnw=311&start=27&ndsp=29&ved=1t:429,r:30,s:0&tx=147&ty=64
Now makes me lose it ... #"%"#$.... how on hell is they intent to
***extend it to discrete GPUs***, when now they are implementing hUMA that then BREAKS when they try to extend to discrete GPUs, because it will have links with the out of arse just for controversy "different memory access times " argument ??????? ... (EDT)
go bug another ... please...