blackkstar :
Yeah, ARM caught up to AMD IPC. You also don't see 5ghz ARM chips, either. IPC is just half the story. The fact that ARM is competing in IPC with an x86 design that is aimed for low IPC, high frequency speaks volumes of how far behind ARM still is. If we could see ARM beating Intel IPC while clocking as high, I would agree that ARM is winning. But it's not.
Wait, are you sure that ARM caugth? Mr. rocks predicted that arm never could caught x86 because x86 is Complex and ARM is Simplex, he also predicted that trillions of ARM cores would be needed to match a single x86 core.
/sarcasm
Now seriously, older 32bit ARM chips caught both AMD and intel IPC. Modern 64bit ARM has surpassed both AMD and Intel IPC.
The new A57 core has about 36% more IPC than jaguar core. Jaguar core has more IPC than Piledriver. Thus first ARM 64 bit core has surpassed the IPC of a mature Piledriver core.
Apple cyclone core IPC is so high that two of them @ 1.3GHz match quad x86 cores @ 1.6GHz from Intel.
ARM chips have already broken the 3GHz.
blackkstar :
AMD is talking about 4ghz for K12, and if we get a 4ghz ARM core, it might compete. But the thermal properties of ARM at that speed will be far different from the 1.5ghz chip in your phone. Meaning that it's going to need a lot more voltage and TDP increases with the square of input voltage. Meaning ARM's advantage can dry up very quickly.
Sure that TDP increases with the square of voltage, but this applies to both x86 and ARM chips, not only to the latter.
Once again...
Keller was very complimentary about the ARMv8 ISA in his talk, saying it has more registers and "a proper three-operand instruction set." He noted that ARMv8 doesn't require the same instruction decoding hardware as an x86 processor, leaving more room to concentrate on performance. Keller even outright said that "the way we built ARM is a little different from x86" because it "has a bigger engine."
An 100W ARM chip will provide more performance than a 100W x86 chip.
blackkstar :
DDR3 is nearly 5 years old now. Of course it's not giving us enough bandwidth. Do you all not remember the transition from EDO -> SDR -> DDR1 -> DDR2 -> DDR3? At the end of life for each one of those technologies people were screaming about how they weren't providing enough bandwidth for something.
DDR4's problem is that it was designed to solve the problem of traditional CPUs not having enough bandwidth and traditional CPUs do have enough bandwidth, we just need more for GPUs.
DDR4 will appear first in servers, whose "traditional CPUs" will benefit from the improved bandwidth. The problem with DDR4 is that its touching the limits of the DDR design and doesn't really aim to solve the CPU memory wall problem.
A solution to the CPU memory wall problem only can be achieved by a revolutionary approach to memory architecture. This is what Intel, ARM, and others members of the HMC consortium are doing. The goal is to provide about
16x more bandwidth than the slow DDR memory. JEDEC attempts that same with the new HBM specification.
Of course GPUs will also benefit from the new ultra-fast memory.