AMD CPU speculation... and expert conjecture

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blackkstar

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This is a problem with bulk.

Look at Intel finFET on bulk. Everyone ran around going "it's all due to the TIM! Haswell could clock just as high as FX and then FX is FINISHED!"

So Intel released Devil's Canyon and everyone found out that the chips hit a massive voltage wall regardless of temps and fell on its face. The same thing that happens to Kaveri on bulk.

Bulk sucks, it doesn't scale with voltage. Look at TSMC too. Tahiti ships at what, a 1.17 core voltage.

Now look at PD-SOI 32nm. It ships about 1.32v stock for FX CPU series yet it can do 1.55v no issue. That's a 17% increase in voltage.

Now look at what happens if you apply 17% voltage increase to TSMC 28nm bulk. You end up with 1.37v. No one in their right mind does that, because the chip stops scaling. My 7970 on water stops scaling with voltage around 1.25v and then I can't do anything else with the chip. It runs all day long at 100% load at 60c.

Meanwhile on PD-SOI, I can bump voltage up to 1.7v (nearly 30% increase in voltage!!), hit higher clocks than I normally could at 1.6v, and then still have a system stable enough with all cores active to putz around Windows.

Show me a bulk product that can live through a 30% voltage increase and still be usable. I'm not talking LN2 runs and then throw the chip away. I'm talking someone doing what a lot of people would consider stupid and living to tell the tale. I consider myself one of those people. I have constantly ran this thing at 1.6v+ for more than a year. And it spends a lot of time in Gentoo, compiled to use every instruction available, at 100% load baking textures and rendering.

If you were right about bulk being so great, Devi's Canyon wouldn't be a massive disappointment. SOI is vastly superior for raw performance when you compare voltage headroom between normal and what the chip can handle without degrading massively.

Also, do you have a source that AMD is abandoning CMT? All I can remember is one article that claims that, but if you read the article, it says nothing about abandoning CMT. It just says a new design. Basically it was a clickbait article.

CMT is like Hyperthreading. You are basically looking at Pentium 4 and going "wow, Hyperthreading sucks, I hope Intel gets rid of it!" And we all know Intel fixed Hyperthreading (for the most part) and their cores. And now Hyperthreading is a premium feature on premium chips. Intel thinks Hyperthreading is so good they want you to pay a lot of extra money up upgrade from 4670k to 4790k.

My point is that there's a lot of things that are wrong with the Bulldozer family, but you're basically isolating one that you dont' agree with and pinning the blame on CMT entirely.

The thing about you saying that "CMT is completely broken" is that you can actually disable CMT on FX chips if your motherboard supports it, by running one core per module. Then, your Piledriver has its own integer units, full access to FPU, full decoder, etc. Yet it doesn't magically blow past Intel when you do that. Do you know why? Why is it when you remove the CMT part of FX chips from the equation that they still lag behind? Do you still think AMD's performance problems all come from CMT?

You just cherry pick information that fits your goals. You got blown out of the water by ARM replacing everything so now you're moving onto the "once AMD abandons CMT they will be so much better!" thing beating the same few sources you've found to death and ignoring every other piece of evidence in existence.

AMD could come back and do extreme CMT with 4 threads sharing a module or something. And it might be awesome (Power with more than two SMT threads per physical core is serious business). You need to realize that just because something has a characteristic that stands out and that thing is not so great, that it doesn't mean that feature that stands out is the cause of the problems. For all you know if Intel used CMT on Haswell, we'd see 8 core consumer Haswells that cost $300, that were just as good as Haswell is now.
 

8350rocks

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I have not got the time to dig, but you can find the info if you are willing to shlep through the old SOI consortium info. The 32nm process AMD used was the last node shrink from 45nm PD-SOI and basically used similar manufacturing processes, hence why they could port a few of the last version of Phenom II to 32nm PD-SOI with little issue. It was the last of the PD-SOI shrinks as well...the next node should have been ~26nm FD-SOI with UTBB and back biasing...but AMD probably saw what happened with Bulldozer on a new technology and said F*** the yield problems we see coming with that, at least with bulk, if they screw that up, we can go somewhere else.

SOI ties them heavily to either IBM or GF. Good luck getting any fab space @ IBM, so that leaves GF. Samsung is going back into SOI these days, but they are likely a full year behind any new node with FD-SOI...so that is out.
 

jdwii

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Why do we continue to argue with juan when he claimed the A10 is equal to a I5 2500K he lost every little bit of credibility he had left, Not to mention he uses fallacious arguments as much as he can. He still can't even show benchmarks in handbrake(other video encoding software) or games where an A10 is equal to a I5 or hell 10% close. Maybe in synthetic benchmarks that benchmarks the IGPU but not just the CPU part of it, Heck in a lot of those benchmarks the A10 7850K is slower then the A10 6800K in CPU tasks. Plus he is another misguided linux fanboy.
I see him personally attack 8350rocks, de5_Roy, and a couple others yet the mods let him? He has a right to be here like everyone else but the attacks and the Juan is the only one right attitude he needs to stop he has been proven wrong before.
 

juanrga

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I don't know if the die shot is Excavator or not. But I know it is not K12.

About 32nm being PDSOI you are entirely right. My mistake!
 

juanrga

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I know you never typed it. That is why I refer to it as "(sarcam -->) "terrible yields" (<-- sarcasm)". Not only you didn't understand the difference between typo and FUD but you don't understand now the difference between sarcasm and lie, despite I gave you dictionary links to each concept. Do I need to repeat the links?

We know the whole die is subject to defects, Capt. Obvious. This is why it was said to you that defects would be first detected in the CPU part because it is less modular, with a 2:8 ratio, than the GPU.

Your pretension that AMD is not releasing full 2M / 512 cores for mobile due to (sarcasm -->) "terrible yields" (<-- sarcasm) is plain wrong. AMD is releasing full 2M / 512 cores for mobile in one of the new FX APUs. The reason why they are clocked lower than desktop parts is because have to fit 35W TDP.

In short, there are three explanations given in this thread on why AMD lowered the clocks for DT:

1. Kaveri 2.0 refresh
2. OEM 95W requirement
3. Carrizo related.

Your (sarcasm -->) "terrible yields" (<-- sarcasm) doesn't count.



As mentioned before, GCN is an improved architecture and doesn't need to be clocked so high as WLIV4 to produce more performance. Kaveri GPU clocks are lower than Richland clocks but Kaveri is faster. The reason why Kaveri GPU clocks are not higher is explained by bottlenecked generated by slow DDR3 memory.

I already explained to you before that AMD original plan was to use GDDR5 memory for Kaveri. That plan was canceled and final Kaveri is less powerful than initially planed.

AMD is currently translating production from TSMC to Glofo, including GCN GPUs

http://www.kitguru.net/components/graphic-cards/anton-shilov/globalfoundries-to-make-semi-custom-apus-cpus-gpus-for-amd/



I don't know whom you pretend to fool (yourself?), but your modus operandi is always the same. You post some nonsense, you are corrected and then you react with personal attacks. The magnitude of the attack is proportional to the magnitude of the correction. You did before, you are doing it now and you will continue to do it in future.



Nope. What you found is the old 28nm SHP process in an ancient 2011 roadmap

600x436px-LL-c248f84e_0i268739sz100.jpeg


but this old "SHP" is the canceled SOI process for FX CPUs

550x126px-LL-1ead8326_shp.png


That is not the actual 28nm SHP used in Kaveri APU. The actual 28nm SHP is a bulk custom process optimized for density.

See? You never know what you are talking about. You only can insult people who correct you :lol:
 

juanrga

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Average OC on air for Trinity, Vishera, and Richland:

A10-5800k: 4.5GHz (32nm SOI)
FX-8350: 4.8GHz (32nm SOI)
A10-6800k: 4.9GHz (32nm SOI)

Average OC on air for Lynnfield, Sandy Bridge, and Ivy Bridge:

i7-880: 4.3GHz (45nm bulk)
i7-2600k: 5.1GHz (32nm bulk)
i7-3770k: 4.7GHz (22nm bulk finfet)

In the first place we can observe that 32nm bulk Intel chips hit higher frequencies than 32nm SOI (including second gen Richland).

5.1GHz bulk > 4.9GHz SOI

Of course SOI has its advantages, but it seems evident that bulk isn't so bad as you pretend.

Now check the Ivy Bridge frequencies: it overclocks poor than sandy bridge despite being in a better node. Haswell and Devilscanyon have the same problem. In fact whereas the ancient 2600k can cross the 5Ghz barrier using air cooling, the new 4790k cannot hit 4.8GHz using water cooling.

Both the old i7-2600k and the new i7-4790k use bulk. Therefore bulk is not the reason why IvyBridge/Haswell/Devilscanyon overclock so bad. Ignoring TIM, FIVR, and other nuisances, the main reason is that the introduction of finfets modified the shape of the voltage curve as shown in next figure

GewwXCn.png


As I wrote before in this thread:



And I expect Skylake to be better if it doesn't have a FIVR again, as rumored.



There are plenty of articles mentioning AMD abandon of CMT. This is one:

Not a lot of details about the new micro-architecture are known at present. What is recognized for sure is that it will drop CMT in favour of some kind of SMT (something akin to Intel’s HyperThreading) technology to improve performance in both single-threaded and multi-threaded cases.

http://www.xbitlabs.com/news/cpu/display/20140510165441_AMD_to_Introduce_New_High_Performance_Micro_Architecture_in_2015_Report.html

You are grossly misinterpreting my position. I am not criticizing CMT because it is in bulldozer. I am criticizing CMT because of its inherent weak points. Bulldozer has its owns flaws beyond using CMT.

Hyperthreading is Intel implementation of SMT. CMT and SMT are rather different approaches. One is rather good the other is not. In fact, whereas SMT is found in many products, CMT is only present in AMD bulldozer family of processors.

CMT is not fixable, because it is not a good approach that needs to be polished. Nobody else is adopting CMT; in fact even AMD rejected it for jaguar.

I find it funny that you accuse me of cherry picking information that fits my goals, when I mentioned an awarded paper from SC13 (SuperComputer 13) that predicts that ARM will replace x86, but you and others here ignore it and its conclusions like if never was published.

And I am not moving anything away from ARM. My last post about ARM was my comment to Cazalan post about the new Thunder-X ARM processor. Since there is no new info and nobody is posting nonsense/FUD about ARM. I stopped posting about ARM. Now that you re-start the topic I am replying you.

Expect AMD to release an improved module with Excavator and then abandon the modular concept for the new K12 architecture.
 

juanrga

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What I claimed about Kaveri A10 is a bit different than you pretend. I already corrected you, and I already gave benchmarks, lots of them, synthetic and not synthetic, open and closed, but you insist in your infinite loop...

I hope that you are kidding about my credibility, otherwise I am sorry to inform you that I don't care a bit about your opinion.

I am realist regarding linux. This is why I left people to try both Windows and linux and then left them select the one that they more like. You call others fanboys but you are the only one who spreads nonsense and myths about linux.

You see what you want see but I am only replying to attacks, as this new one from you.
 

jdwii

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No again you go around and say other wise you more then once said the A10 will be around the I5 2500K level but you continue to dismiss it again making you less credible, As for your Linux nonsense yeah have fun with that one, must be nice to always defend the minority, Its seriously like arguing with a religious person when it comes to you.
 

so you finally admit to lying and trolling. you got caught and now you're "tagging" it trying in futility to pass it off as sarcasm.

i do understand what's what. that's why i called you out and showed you where you're lying. i really wish you cease lying and adding lies and trolling me to cover the lies. you're been found out long time ago when i pointed out your lies.

it doesn't matter where a defect is found "first". only matters that a defect is found, then amd decides how to bin the chip. i recall that more knowledgeable people explained to you in details how chip binning works after we found out that you knew nothing about chip manufacturing. do try to recall those.

oh wow. another one of yous Lies comes out. no, "tagging" sarcasm won't work, as usual. i never even pretended anything. my assumption is based on publicly available information. i already mentioned that amd would lower clocks for mobile skus to fit into lower tdp, which is needed to fit into laptop class devices. clock lowering is only part of the yield issues, another part is lack or fully enabled apu dies that fit into that low tdp.

kaveri 2.0 refresh is likely and the reason would be.... guess what? the reason would be glofo's failure in tuning their 28nm shp bulk process to maintain good yields. that's the reason also likely to affect carrizo launch as well.

ofc it doesn't count - because I Never Said That. now stop lying and try to engage in non-fallacious, logical and relevant discusssion/argument.

got nothing to do with glofo's performance with fabbing kaveri. quite trying to segue. for more, read below.

once again, nothing to do with fabbing kaveri. moreover, production hasn't started yet. as for console socs, those are amd semi-custom designs i.e. amd isn't the sole owner. those are more portable by design, too.
if amd was confident, they'd have glofo fab those earlier gcn gpus in 2011. now they'd have to wait till glofo has ironed out their 28nm problems - which, kaveri production is currently facing. however, gpus alone will have easier time since those are fabbed on mobile nodes... still, i'll wait till glofo has actually started volume production of gpus before coming to any conclusion.


right back at you. :D

actually, my m.o. for dealing with you is always the same. i argue ideas, point out fallacies, avoid trollbaits, call out lies wherever i find one and explain how you're lying. at least i try to. if you had actually tried healthy, logical, technical argument it'd be different.

uh, that's exactly what You've been doing to me (and to others.. but that's others' problem, not mine) this whole time. now you're Lying about that again and putting it on me. that won't work. i only point out (with explanation) where you're lying. and that's when you cry "personal attack".

i didn't do any calculation about any magnitude, i only pointed out mistakes, misunderstanding, fallacies and lies and trolling wherever i found. simple.
and.. how do you predict what i'd be doing in the future. unless... you'd be doing the same lying and trolling you're doing now because that's the only way i'd be pointing those out as i've been doing at present. :D why not cease these sick behaviors and try engaging in healthy arguments?



quote-emphasis mine. that is a great find, juan. i totally missed that old 28nm shp being soi. thanks to you, i can re-enforce glofo's incompetence to build a decent soi process for kaveri. no wonder they failed and went for bulk (greedy cheapskates). how am i insulting you for finding out vital info that i missed before? i only point out lying and trolling where it happens.
 

wh3resmycar

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oh links that you've posted, i thought mine.

well sorry i usually redact things that i quote and just focus on the statements.. the links you posted are "speculations", try to understand how I used the word "Are" with "actually" in my reply. and learn to understand and comprehend the articles you're reading. e.g. link #2's title includes the word "PROBABLY" (other words like: "aims", "expects" can be found on the other links you've posted). you're mistaking a probable scenario as fact.

again for the sake of what's actually and in fact out there, APUs "are" for cheap gaming.




 
AMD reveals specs of new desktop kaveri APUs
http://www.cpu-world.com/news_2014/2014060601_AND_reveals_specs_of_new_desktop_APUs.html
seems like yields might be finally improving. or they've stockpiled enough chips to make them available in retail.

check out these two bad boys:
Model No. of Cores Frequency /Turbo L2 cache Graphics Model No. Radeon cores iGPU Frequency Memory TDP
A8-7600 4 3.1 / 3.8 GHz 4 MB R7 series 384 720 MHz DDR3-2133 65W
A10-7800 4 3.5 / 3.9 GHz 4 MB R7 series 512 720 MHz DDR3-2133 65W

a10 7800, same tdp as a8 7600 that impressed reviewers, has full range of shaders, 2133 ram support and higher cpu clockrate. no -k, so prolly no unlocked multiplier. previously, trinity and richland launches had these lower tdp apus (a10 5700, 6700 et al) accompanied by their unlocked flagships. i haven't found msrp info yet.

edit3: according to cpu-world
http://www.cpu-world.com/CPUs/Bulldozer/AMD-A10-Series%20A10-7800.html
the a10 7800 non-k can be configured to run at 45w tdp. same configurable tdp as a8 7600. wut!! this'll make for some very interesting small size steam box/htpc/gaming htpc comparisons.

edit4:
VR-Zone sits down with AMD’s embedded boss Scott Aylor to talk about AMD’s push into the world of embedded processing.
http://vr-zone.com/articles/can-amd-make-way-embedded-market/78972.html
 

colinp

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For every major release since Bulldozer, CPU or APU, the top binned part has stayed the top, excluding those absurd 9000-something Piledrivers. It would be a bit of a departure then for AMD to release a faster Kaveri, except as a Richland-style refresh. (Any bets at to what that'll be called? My money is on... "Carrizo"...) Still, it'll be interesting to see if any Kaveri-Athlons get released, though I don't expect them to break any records either.
 

they can do what they did with richland, refresh the existing lineup and recycle an old codename. richland used to be the codename for lower end trinity apus. right now, amd doesn't have any codename left out since all kaveri apus bear the same codename. amd's apus bear codenames based on rivers. they earlier cancelled an apu called krishna... that and kaveri both are indian rivers, so krishna may be a candidate. but kaveri 1.1/2.0 will be a reality only if exc-based apus get pushed back or cancelled or amd decides to use sr-a cores for apus.
if amd follows their past trend, kaveri-athlons will launch much later in the cycle.
 

szatkus

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Don't feed the troll.
This thread would be much more readable if everyone just started ignoring Juan.
 

colinp

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I've been internally debating for some time now to say the same. But then there's a certain sadistic side to me that enjoys our resident troll making a fool of himself. But I am surprised that this has been allowed to go on as long as it has done by now.

Moderating isn't hard. If you can see a discussion getting out of hand, and identify if there is a single nexus causing it, then you warn; and if that isn't heeded, you sin bin them for a bit. In this case, it's easy. If you could take out a single person from this thread for a while to stop the antagonism, who would it be?
 

etayorius

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I don`t see Juan breaking any rule, he may be extremely arrogant and stubborn but he is within the rules, if anything you all love to gang against him for anything he writes... if he is wrong or right it is quite irrelevant, most of you are not smart enough to ignore him.
 

colinp

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I personally didn't name anyone, but you obviously had someone in mind...

General incivility, passive-aggressive behaviour, accusations of reading comprehension failure, insinuation that other people are just plain stupid for not understanding: I can see why these might not be "rules" as such. It seems like you only get a warning here for calling someone a twunt or by going off topic.

Mostly everyone here can get along fine. Disagreement is fine, discourse can be polite, if a little heated at times; that's how it should be - agree to disagree and all that.

But I do agree with your gist that if someone annoys you or if you think they are trolling, then the best way to deal with it is to just ignore them.

DFTT - Don't Feed The Troll
 

8350rocks

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SB overclocked much better in terms of X frequency on air cooling, however, the voltage required to get there was much higher as well...(higher leakage in the chip due to bulk). Now, what we see with the newer chips is a "voltage wall" where no matter what, you cannot get the chip to run stable past X point based entirely on how good the silicon you got was.

Ultimately what it boils down to be is that Bulk process is the limiting factor. FinFETs change the curve, I grant you that, but that is not the reason that the overclocking is limited in the newer chips. Additionally, combining bulk process with higher density designs decreases the capability to overclock a given architecture. As chips become more complex, and more dense in their designs, we will see less and less successful overclocks of incredibly high margins.
 

Cazalan

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Where have you seen a Devil's Canyon review? It's a bit early to say "everyone" when the parts haven't officially started shipping yet.

Edit: I suggest responding in the Intel thread. Less drama there. ;)

http://www.tomshardware.com/forum/id-1581001/intel-future-chips-news-rumours-reviews/page-9.html#13448758


 

just when i was getting used to the peace and quiet over there... :p
d.c. cpus seem to be subject to the same silicon lottery as older haswells. so improved t.i.m. and power delivery might not help much if the die isn't o.c. friendly.

anywho, i've read several articles that say amd apus use cheaper t.i.m. under their heatspreader compared to the fx cpus. with chip density rising (kaveri being significantly denser than richland), dt apus might need better quality t.i.m. soon.

edit: nvm.
 
i could use some clarification about this:
http://www.anandtech.com/show/7702/amd-kaveri-docs-reference-quadchannel-memory-interface-gddr5-option
says here that kaveri has 4 (x 64 bit) memory controllers, capable of ddr3 and gddr5 mode. basically, 256 bit total bit width for ddr3 or gddr5 ram. i understand that a new socket may be needed for gddr5 use.

but. if a new socket would be needed anyway for gddr5, would it be possible to use 2 of the m.c. for ddr3 and 2 for gddr5? 128 bit for ddr3 and gddr5 each. system memory gets usual 28 bit for ddr3 while mobo manufacturers add 1-2 GB (total) on the p.c.b.
since it'd be hard and uneconomic for desktops, would it be possible for laptops/bga apus? 128bit for gddr5 doesn't sound uneconomic to me since it'd cost half ( i think) as much to print 128 lines to the vram chips. boards makders could get away using cheaper ram ics.

would it break hsa if the pc was to treat system memory and discreet video memory as the same pool? since kaveri already had internal components for hsa.

this is only for kaveri. i guess when carrizo comes out with it's ddr3/4 imc, this memory bw issue would be alleviated. ddr4 should be able to provide with high bw at low latency making gddr5 moot.
 

anxiousinfusion

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A bunch of sources say "DDR4 is 50% higher bandwidth over DDR3". Maybe I suck a maths but isn't 4266 a 100% increase over 2133? I thought DDR4 essentially doubles bandwidth.
 

ddr4 has other advantages, mainly it uses less power than ddr3 (~1.2v vs 1.35-1.5). ddr4 can also use hbm memory, various stacking techs to increase density and a lot of other stuff that went over my head. if the imc is 64bit, then ddr4 1600 and ddr3 1600 will have the same bw, afaik. bw will double if number of channels double (maintaining the same speed) or if clockrate doubles (maintaining the same number of channels).
edit: according to wikipedia the voltage range for ddr4 is 1.05-1.2v, starting with ddr4 2133 vs ddr3's 1.2-1.65v.
another advantage would be memory bank switching. i don't know much about this one.
 

juanrga

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My claims about Kaveri and i5-2500k were very accurate: final measurements depart from my early predictions by only single digit percents.

As mentioned in a recent tomshardware article, windows has less market share than linux. Windows is the minority OS.



What I said is that if defects exist, they would appear first in the less modular part. The fact they are not appearing in the CPU implies that the yields are very good.

The hypothetical Kaveri 2.0 refresh was mentioned as possible competition against Haswell refresh to satisfy inversors/analysts/market. It is not about having terrible initial yields.

The reason why I did bring Carrizo to the options has nothing to do with terrible yields either.

AMD migration of products to Glofo is related to the predicted ~10% drop of the PC market and the need to satisfy the WSA.

The reason why AMD chose bulk has nothing to do with Glofo competence/incompetence. SOI cannot provide the high densities needed for GCN. The link given before explicitly mentions that the original process was designed for "CPUs".




The links that I posted mention the new business APUs. AMD has been selling professional APUs during years

http://news.softpedia.com/news/AMD-s-FirePro-APU-Trashes-Intel-s-Xeon-E3-in-First-Official-Benchmarks-285487.shtml

Those professional/business APUs are not for cheap gaming. The new Berlin APU for servers is not for cheap gaming:

http://arstechnica.com/information-technology/2014/04/amd-demos-hsa-for-the-server-room-with-java-on-top/

http://www.theregister.co.uk/2014/04/16/amd_demos_berlin_its_first_heterogeneous_system_architecture_opteron_at_red_hat/




Those are (business) parts of previously announced desktop models. Again unrelated to yields.




The change in the voltage shape is the reason for the voltage wall, which appears at the crossing point between 22nm-FF and 32nm-PLN curves. The crossing point only appears once and will not repeat at 14nm-FF.

I suppose the existence of this crossing point is the reason why Glofo/TSMC/Samsung/IBM/... introduce finfets at 14/16nm and not earlier. AMD will not suffer from voltage wall when migrating from 28nm-PLN (Kaveri/Carrizo) to 14nm-FF (K12).

I expect Broadwell-K back on the 5GHz range if Intel doesn't change anything else.




For instance in this thread. Link given by me. The reviewer couldn't hit 4.8Ghz on water. That is very far from the advertised "over 5.5GHz on air".




Kaveri doesn't have GDDR5 controller.

GDDR5 and DDR3 modes are incompatible. The original plan was to use either DDR3 or GDDR5 as system ram.

HSA relies on hUMA. Your "system memory and discreet video memory" are not "the same pool" and breaks HSA.

GDDR5 has about the same latency than DDR. DDR4 doesn't provide the same BW than GDDR5, and will not replace GDDR5. Moreover, the high-frequency DDR4 modules --e.g., 4266MHz-- will only appear at latter times. DDR4 starts at 2133MHz, thus will provide the same BW than current DDR3-2133MHz.




No. DDR4 cannot "use hbm memory". DDR4 and HBM are two completely different standards.
 
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