Yes, IIRC, somewhere in the original white papers, they had fleshed out MCs for both DDR3 and GDDR5, though the consensus was you would get one or the other. Both would not be feasible, and it was still limited to a maximum of 2 channels. They could pull a MCM opteron configuration out and do the quad channel memory again with the APUs. Though I suspect that will not happen any time soon, if at all.
Basically in the DT APUs, they have the capability to use that MC down the road, the channels for GDDR5 look as though they were put in, though not activated. This is perhaps a nod to how close they were to utilizing that option down the road.
I may have to go dig up some in depth technical info on the Kaveri APUs and see if I can find reference to the GDDR5 MC and whether or not it was cut from the final design or left in to save time.
What I said is that if defects exist, they would appear first in the less modular part. The fact they are not appearing in the CPU implies that the yields are very good.
i don't really understand why you're stuck to the cpu only and completely ignoring the igpu. the apu has both cpu and igpu, and other components. if a defect turns up in the igpu then amd will have to fuse off that portion and bin it accordingly. i keep bringing up the igpu as well because that is denser than the cpu in kaveri apus, and considering glofo's track record fabbing apus and gpus, is as much if not more prone to defects.
juanrga :
The hypothetical Kaveri 2.0 refresh was mentioned as possible competition against Haswell refresh to satisfy inversors/analysts/market. It is not about having terrible initial yields.
The reason why I did bring Carrizo to the options has nothing to do with terrible yields either.
i understand what you're saying. just in case, once again, I Never said anything about yields being terrible at glofo - that'd be a different discussion/argument.
continuing: yield issues would cause a ripple effect and affect both kaveri sequel (if it exists) and carrizo. glofo's 32nm problems affected bd and llano launches, 28nm problems affected kaveri's launch.
juanrga :
The reason why AMD chose bulk has nothing to do with Glofo competence/incompetence. SOI cannot provide the high densities needed for GCN. The link given before explicitly mentions that the original process was designed for "CPUs".
amd didn't choose bulk. they're fabless and are at the mercy of foundries. according to the info you pointed out, glofo failed to build a decent-enough SOI node for high performance mainstream apus/cpus/asics which led to shp-bulk for amd. it's not that SOI can't provide densities, it's glofo's SOI process that couldn't provide the densities..or from the events - workability, lol. a wafer agreement was already in place, so amd had to make do. they had already been bleeding money to glofo.
juanrga :
Those are (business) parts of previously announced desktop models. Again unrelated to yields.
a10 7800, a-something 7400k et al aren't corporate-aimed, they're mainstream consumer apus. besides, business-aimed apus are no different from mainstream consumer ones except in terms of after sales support and minor sku-ing tweaks like configurable tdp. previously, lower tdp, non-k apus always launched alongside flagship ones. this time they didn't. moreover, considering business skus, too - this more or less confirms glofo having problems with their 28nm bulk shp since it took amd so long (counting how much delay amd already faced before launch) to even announce these parts.
juanrga :
Kaveri doesn't have GDDR5 controller.
the launched product doesn't have it enabled. so in a way, yes.
juanrga :
GDDR5 and DDR3 modes are incompatible. The original plan was to use either DDR3 or GDDR5 as system ram.
i haven't seen anywhere that confirms that. i am wondering if two of the imc could be used for ddr3 and the other two for vram i.e. split the 4 imc in 2x for each type.
juanrga :
HSA relies on hUMA. Your "system memory and discreet video memory" are not "the same pool" and breaks HSA.
can memory virtualization work? iirc current system memory access is virtualized. so all it'd need is a tuned virtualization scheme.
juanrga :
GDDR5 has about the same latency than DDR. DDR4 doesn't provide the same BW than GDDR5, and will not replace GDDR5. Moreover, the high-frequency DDR4 modules --e.g., 4266MHz-- will only appear at latter times. DDR4 starts at 2133MHz, thus will provide the same BW than current DDR3-2133MHz.
since carrizo will be in pcs that use ddr4, dual channel ddr4 2133 will likely provide decent amount of bw for the igpu. ddr4 2133 will be the lowest spec ddr4, though. i am expecting ddr4 3000 and higher to become available in time for carrizo's launch. at dual channel, ddr4 won't approach gddr5's bw, but it can certainly provide decent amount of bw as long as amd implements a high-performing imc.
juanrga :
No. DDR4 cannot "use hbm memory". DDR4 and HBM are two completely different standards.
from what i've read so far, hbm is the dram i.c with 128bit ddr interface. ddr4 is the interface, with specs for connecting dram chips. hbm uses ddr interface. ddr4 supports 3d stacking. i don't see why these two cannot be united in holy matrimony... not right now, but in the future.
Yes, IIRC, somewhere in the original white papers, they had fleshed out MCs for both DDR3 and GDDR5, though the consensus was you would get one or the other. Both would not be feasible, and it was still limited to a maximum of 2 channels. They could pull a MCM opteron configuration out and do the quad channel memory again with the APUs. Though I suspect that will not happen any time soon, if at all.
Basically in the DT APUs, they have the capability to use that MC down the road, the channels for GDDR5 look as though they were put in, though not activated. This is perhaps a nod to how close they were to utilizing that option down the road.
I may have to go dig up some in depth technical info on the Kaveri APUs and see if I can find reference to the GDDR5 MC and whether or not it was cut from the final design or left in to save time.
The info that I have is that the GDDR5 memory controller is on die, but is actually fused-out. This could explain why AMD has refused to provide detailed die shot of Kaveri.
It is worth mentioning that the reason why GDDR5 support was dropped is because one of the suppliers of the GDDR5m modules was out of business. This is why Carrizo only includes DDR3/4 support.
de5_Roy :
i don't really understand why you're stuck to the cpu only and completely ignoring the igpu. the apu has both cpu and igpu, and other components. if a defect turns up in the igpu then amd will have to fuse off that portion and bin it accordingly. i keep bringing up the igpu as well because that is denser than the cpu in kaveri apus, and considering glofo's track record fabbing apus and gpus, is as much if not more prone to defects.
amd didn't choose bulk. they're fabless and are at the mercy of foundries. according to the info you pointed out, glofo failed to build a decent-enough SOI node for high performance mainstream apus/cpus/asics which led to shp-bulk for amd. it's not that SOI can't provide densities, it's glofo's SOI process that couldn't provide the densities..or from the events - workability, lol. a wafer agreement was already in place, so amd had to make do. they had already been bleeding money to glofo.
a10 7800, a-something 7400k et al aren't corporate-aimed, they're mainstream consumer apus. besides, business-aimed apus are no different from mainstream consumer ones except in terms of after sales support and minor sku-ing tweaks like configurable tdp. previously, lower tdp, non-k apus always launched alongside flagship ones. this time they didn't. moreover, considering business skus, too - this more or less confirms glofo having problems with their 28nm bulk shp since it took amd so long (counting how much delay amd already faced before launch) to even announce these parts.
i haven't seen anywhere that confirms that. i am wondering if two of the imc could be used for ddr3 and the other two for vram i.e. split the 4 imc in 2x for each type.
can memory virtualization work? iirc current system memory access is virtualized. so all it'd need is a tuned virtualization scheme.
since carrizo will be in pcs that use ddr4, dual channel ddr4 2133 will likely provide decent amount of bw for the igpu. ddr4 2133 will be the lowest spec ddr4, though. i am expecting ddr4 3000 and higher to become available in time for carrizo's launch. at dual channel, ddr4 won't approach gddr5's bw, but it can certainly provide decent amount of bw as long as amd implements a high-performing imc.
from what i've read so far, hbm is the dram i.c with 128bit ddr interface. ddr4 is the interface, with specs for connecting dram chips. hbm uses ddr interface. ddr4 supports 3d stacking. i don't see why these two cannot be united in holy matrimony... not right now, but in the future.
I am not ignoring the gpu. Stop lying. I am saying that defects, if they exist appear first in the less modular part. The less modular part is not the GPU but the CPU, with a ratio of 2:8.
AMD chose bulk by several reasons, from providing a clear migration path to future finfet technology on 14nm/16nm node, to density requirements, including also reduction in costs from porting designs forward and back among foundries.
The A10-7800 and other mainstream consumer APUs were announced on January:
The new desktop APUs presented now by AMD are the business versions, e.g. the A10PRO-7800B.
The GDDR5 memory controller is incompatible with the DDR3 memory controller.
HSA requires both software and hardware elements. A HSA-enabled memory controller is one of the hardware requirements.
Dual channel DDR4-2133 will provide the same bandwith than existent dual channel DDR3-2133, which means that the GPU will continue being bottlenecked.
DDR3-3000 and faster modules are available today. The question is not if DDR4 will be available for Carrizo launch. The question is which will be the prize?
DDR4 looks as patch rather than a real solution for APUs. Future quad-channel DDR4-4266MHz (Carrizo will dual-channel) provides only a fraction of the total bandwidth available to the PS4 APU. The solution is stacked RAM. AMD is developing HBM. ARM is developing a much faster standard: HMC.
The 10--20 TFLOP APUs that AMD and Nvidia want release in future use stacked RAM.
Intel has been increasing the TDP of its top quad-core. The new devilscanyon i7 increases the TDP again. According to recent leaks the top Skylake APU will be rated at 95W
I think this gives further support to your hypothesis of AMD downrating Kaveri to 95W to satisfy OEMs thermal slots. In fact the above table shows slots that coincide with current Kaveri line: 95W, 65W, 45W, 35W...
Intel has been increasing the TDP of its top quad-core. The new devilscanyon i7 increases the TDP again. According to recent leaks the top Skylake APU will be rated at 95W
I think this gives further support to your hypothesis of AMD downrating Kaveri to 95W to satisfy OEMs thermal slots. In fact the above table shows slots that coincide with current Kaveri line: 95W, 65W, 45W, 35W...
Where did you get that from?
Anyway, is HMC a type of chip or a type of interconnect? If it is "just" a type of new chip manufacturing technique, then I would say it can fit in any DDRx standard as long as it fits the interconnects. If it is a new way to interface the chips (interconnect), then it will be up to JEDEC to see if they include it or not; last thing I know is that DDR4 is officially closed as a standard (no new stuff can be added until DDR5, AFAIK) and only revisions can be added.
Well, as long as AMD gets faster RAM, I won't care one way or the other to be honest
since carrizo will be in pcs that use ddr4, dual channel ddr4 2133 will likely provide decent amount of bw for the igpu. i am expecting ddr4 3000 and higher to become available in time for carrizo's launch.
de5_Roy :
DDR4 looks as patch rather than a real solution for APUs. Future quad-channel DDR4-4266MHz (Carrizo will dual-channel) provides only a fraction of the total bandwidth available to the PS4 APU.
Both of you have probably already read up on this but have since forgotten that DDR4 will not operate in traditional dual/quad channels. That has been given up for a point-to-point approach and new DDR4 memory controllers will need a channel for each individual DIMM.
Also, DDR4 3000 and higher will be available for Carrizo's launch as ADATA and a few other manufacturers have 3000MT/s+ products planned.
Both of you have probably already read up on this but have since forgotten that DDR4 will not operate in traditional dual/quad channels. That has been given up for a point-to-point approach and new DDR4 memory controllers will need a channel for each individual DIMM.
Also, DDR4 3000 and higher will be available for Carrizo's launch as ADATA and a few other manufacturers have 3000MT/s+ products planned.
The number of channels is a different issue to the number of DIMMs per channel. Also, I believe that if you want to run the very highest frequency of memory with an AMD chip, then they recommend that you run one DIMM per channel in any case - something to do with voltage and/or stability I think.
Anyone who remembers when DDR3 was introduced will know that the new memory tech is priced very high for quite some time after introduction. As DDR4 hasn't even been introduced to consumers yet, you can be it will be expensive by the time AMD introduces their next generation. I expect that motherboard makers will default to DDR3 initially, as DDR4 would make an AMD system very uncompetitively priced unless somehow they manage to reach - say - i5-2500k levels of performance.
i didn't lie, never started lying in the first place. i pointed out that you have never even mentioned that the igpu can have defects and keep repeating that the yields are "extremely good" because if defects exist they'd show up in the cpu "first" -which is irrelevant because a die with defective igpu is subject to lower binning than a die with fully functional cpu and igpu. that's why fx7600p is the top mobile sku and a10 7850k and 7800 are top dt skus. defects in the igpu relegates dies to lower binning like 7700k. it doesn't matter where defects show up "first" because the whole die is subject to binning. defects don't have a race to finish line where if a defect is found "later" "outside" the cpu area and it'll still be considered higher bin.
for future references, if you're gonna accuse me of lying, specify and explain instead of throwing accusation. i did say that i didn't understand - and that's exactly what happened. if i am not understanding your statement, it's a misunderstanding at best. in addition to that, if you're gonna stick to your claim, try providing credible explanation or let's leave it here. or ask others who might know better about how chips are binned.
juanrga :
I am saying that defects, if they exist appear first in the less modular part. The less modular part is not the GPU but the CPU, with a ratio of 2:8.
defect do exist due to glofo having issues with their process, and they show up as less functional components, reduced clockrates and so on. being modular has nothing to do with it. both cpu and igpu are modular (as in design) not comparative to one another.
juanrga :
AMD chose bulk by several reasons, from providing a clear migration path to future finfet technology on 14nm/16nm node, to density requirements, including also reduction in costs from porting designs forward and back among foundries.
may be. i am not dismissing the additional reasons. but along with the rank incompetence from glofo for failing to build a decent soi node, and then having problems despite switching to bulk, after long delays.
juanrga :
The A10-7800 and other mainstream consumer APUs were announced on January:
http://www.hardwarepal.com/second-kaveri-lineup-q2-2014-a10-7800-a6-7400k-a4-7300/
http://www.thinkcomputers.org/amd-a10-7800-kaveri-apu-benchmarked-against-a10-6800k/
The new desktop APUs presented now by AMD are the business versions, e.g. the A10PRO-7800B.
nice catches. i didn't bother searching for additional info on kaveri back then. i just realized that the first link was right at the end of the first page of search results when i was looking for info, lol.
the first link: i missed that one. seems like the writer extrapolated the model number and skus from 7850k specs and past trends. even though the announcement of 7800 non k is a logical next step after 7850k's, i figured that glofo's process issues hindered amd from formally announcing them. the article doesn't show or mention any official relation to amd announcing the 7800 et al apus. if i consider it credible, the article speculates that these apus would be available in march or by april and will have ddr3 2400 support - makes the whole thing unofficial. and the writer can't speculate clockrates - there's a hint. especially the last bit indicates that while amd may have chips in the house, they didn't have enough to formally announce (back in jan. hence the q2 goal) the models and had to stockpile them for longer - once again pointing to process and yield issues. i call the latest launch official because it has fully detailed information except prices and retail availability for consumer skus (although a8 7600 price was announced as $120~ during launch).
the second link: not much to say here, it's just benchmarks. likely from early e.s. iirc the sample's heatspreader read "7800 series". got nothing to do with glofo's problems.
as an aside, i don't know if wccfghiripoffothersitesthatgetfirstdibsontech.com ripped off hardwarepal or the other way, they did include a10 7800 price - $172. even they wouldn't speculate clockrates.
i am yet to see the new apus on newegg.
juanrga :
The GDDR5 memory controller is incompatible with the DDR3 memory controller.
yes. and they don't need to be compatible with each other to access respective memories as the vram is treated as the local memory for igpu i.e. treated as how discreet gfx care treated. however, from huma and heterogenous queuing - both cpu and igpu should be able to access each other's memory space, so accessing ddr3 and gddr5 shouldn't be an issue regardless of controller. when i tried to speculate a gddr5-enabled kaveri before, i didn't understand the presence of gddr5 mode or 4 dcts (dram controllers). now it helps me refining that speculation.
juanrga :
HSA requires both software and hardware elements. A HSA-enabled memory controller is one of the hardware requirements.
that's okay.. actually makes using the vram and system ram pooling easier.
juanrga :
Dual channel DDR4-2133 will provide the same bandwith than existent dual channel DDR3-2133, which means that the GPU will continue being bottlenecked.
i though that was understood. but ddr4 2133 will provide the performance at lower voltage and allow for future speed improvements. nowhere near gddr5 level bw, but higher than ddr3 1600-1866 available today.
juanrga :
DDR3-3000 and faster modules are available today. The question is not if DDR4 will be available for Carrizo launch. The question is which will be the prize?
http://cdn2.wccftech.com/wp-content/uploads/2013/11/DDR4-memory-pricing-635x466.png
pricing is highly flexible and dependent on market factors, irrelevant to my speculations.
juanrga :
DDR4 looks as patch rather than a real solution for APUs. Future quad-channel DDR4-4266MHz (Carrizo will dual-channel) provides only a fraction of the total bandwidth available to the PS4 APU.
to me, ps4 comparisons are useless as that soc is a customized solution for a fixed device. i was comparing my imaginary kaveri to 7850k and a10 6800k as baselines.
juanrga :
The solution is stacked RAM. AMD is developing HBM. ARM is developing a much faster standard: HMC.
i don't know much about hmc yet. imo, on-package edram can help e.g. crystal well in intel iris pro igpu. but stacked ram... it may affect overall yields (depends on type of stacking). as newly obtained info shows, glofo will fail even harder in the begining . tbh, i am still learning about 3d stacking but the potantial looks very promising.
juanrga :
The 10--20 TFLOP APUs that AMD and Nvidia want release in future use stacked RAM.
well.. good for them, if it's true.
anxiousinfusion :
de5_Roy :
since carrizo will be in pcs that use ddr4, dual channel ddr4 2133 will likely provide decent amount of bw for the igpu. i am expecting ddr4 3000 and higher to become available in time for carrizo's launch.
Both of you have probably already read up on this but have since forgotten that DDR4 will not operate in traditional dual/quad channels. That has been given up for a point-to-point approach and new DDR4 memory controllers will need a channel for each individual DIMM.
Also, DDR4 3000 and higher will be available for Carrizo's launch as ADATA and a few other manufacturers have 3000MT/s+ products planned.
Anyway, is HMC a type of chip or a type of interconnect? If it is "just" a type of new chip manufacturing technique, then I would say it can fit in any DDRx standard as long as it fits the interconnects. If it is a new way to interface the chips (interconnect), then it will be up to JEDEC to see if they include it or not; last thing I know is that DDR4 is officially closed as a standard (no new stuff can be added until DDR5, AFAIK) and only revisions can be added.
Well, as long as AMD gets faster RAM, I won't care one way or the other to be honest
Cheers!
The skylake leak is now reproduced in several forums and tech sites. It has been also leaked that Intel abandon IVR.
HMC is a revolutionary memory technology that defines new modules, interconnect, topologies, logic... Whereas DDR4 is an evolution of DDR3, HMC iis a complete paradigm shift from current memory architectures.
You can find further info (including FAQ) in the HMC consortium site
http://www.hybridmemorycube.org/
Intel, ARM, Nvidia, Samsung, Micron Technology, HP, Microsoft... are members of HMC.
Yes, HBM will be fast, but one of the reasons why I prefer HMC is because it is much faster.
Anyway, is HMC a type of chip or a type of interconnect? If it is "just" a type of new chip manufacturing technique, then I would say it can fit in any DDRx standard as long as it fits the interconnects. If it is a new way to interface the chips (interconnect), then it will be up to JEDEC to see if they include it or not; last thing I know is that DDR4 is officially closed as a standard (no new stuff can be added until DDR5, AFAIK) and only revisions can be added.
Well, as long as AMD gets faster RAM, I won't care one way or the other to be honest
HMC is cool stuff but it is in a rapid development phase. A number of early adopters have kicked off projects using it. The cost is still very high so you'll initially only see it in HPC and other expensive platforms. The interconnect is high speed serial I/O, similar to PCIe/SATA but faster (10-30GT/s vs PCIe 3.0 of 8GT/s per lane).
So far only Micron is making the HMC parts. They're sampling 2nd generation parts but already making a 3rd generation which is faster/denser. Fujitsu has a HPC board where they have 3 CPU sockets and 8 HMC sockets. With a top capacity of 4GB right now that limits their board to 32GB of memory, although very fast memory. Overkill for a consumer PC but rather low for a server.
Right now it's like hitting a moving target as Micron may stabilize on Gen3 as the sweet spot. I wouldn't expect to see it in consumer grade hardware for a few years.
Both of you have probably already read up on this but have since forgotten that DDR4 will not operate in traditional dual/quad channels. That has been given up for a point-to-point approach and new DDR4 memory controllers will need a channel for each individual DIMM.
Also, DDR4 3000 and higher will be available for Carrizo's launch as ADATA and a few other manufacturers have 3000MT/s+ products planned.
I cannot talk by him, but I know the new topology of DDR4. It doesn't change what I said. Dual-channel DDR4 mobos will use two slots and quad-channel mobos will use four slots.
Yes, it is possible that DDR4-3000 will be available for Carrizo's launch, but the BW is the same that you can obtain today with DDR3-3000 modules and the key here will the cost. Check the figure that I shared before. DDR4 is not expected to be cheaper than DDR3 before Q1 2016.
Well, I don't know how big the market would be, but remember there was people who bought the RD RAM back in the day with the ABSURD price difference from DDR1 at the time, just because Intel put it down people's throats.
Also, the HMC page reads just like RD RAM back in the day... They're promising a new life and paradise, but... At a cost
Well, I don't know how big the market would be, but remember there was people who bought the RD RAM back in the day with the ABSURD price difference from DDR1 at the time, just because Intel put it down people's throats.
Also, the HMC page reads just like RD RAM back in the day... They're promising a new life and paradise, but... At a cost
Cheers!
I agree on that some people will jump on the DDR4 bandwagon very early, despite prices. I was considering mainstream adoption.
Of course, HMC will be very expensive before becomes mainstream, but the extra cost is justified because this new technology provides a quantum leap over current memory technologies. E.g. We are talking about BW of 2TB/s and higher...
i pointed out that you have never even mentioned that the igpu can have defects and keep repeating that the yields are "extremely good" because if defects exist they'd show up in the cpu "first" -which is irrelevant because a die with defective igpu is subject to lower binning than a die with fully functional cpu and igpu.
to me, ps4 comparisons are useless as that soc is a customized solution for a fixed device. i was comparing my imaginary kaveri to 7850k and a10 6800k as baselines.
I have considered GPUs since the first minute that I have discussed defects. Don't lie. I have been saying you that if defects exist they appear first in the >>>> less modular part <<<< of the APU. It is evident that the less modular part is not the >>>> GPU <<<<, but the CPU, with a ratio of >>>> 2:8 <<<<.
I am comparing to PS4 APU, by two reasons (i) because this is the fastest APU made by AMD at this moment and (ii) because it uses GDDR5 for system memory. This makes it relevant to discuss the more powerful Kaveri APU with GDDR5 for system memory that AMD had planned initially and that is mentioned in AMD internal docs.
check out these two bad boys:
Model No. of Cores Frequency /Turbo L2 cache Graphics Model No. Radeon cores iGPU Frequency Memory TDP
A8-7600 4 3.1 / 3.8 GHz 4 MB R7 series 384 720 MHz DDR3-2133 65W
A10-7800 4 3.5 / 3.9 GHz 4 MB R7 series 512 720 MHz DDR3-2133 65W
a10 7800, same tdp as a8 7600 that impressed reviewers, has full range of shaders, 2133 ram support and higher cpu clockrate. no -k, so prolly no unlocked multiplier. previously, trinity and richland launches had these lower tdp apus (a10 5700, 6700 et al) accompanied by their unlocked flagships. i haven't found msrp info yet.
edit3: according to cpu-world http://www.cpu-world.com/CPUs/Bulldozer/AMD-A10-Series%20A10-7800.html
the a10 7800 non-k can be configured to run at 45w tdp. same configurable tdp as a8 7600. wut!! this'll make for some very interesting small size steam box/htpc/gaming htpc comparisons.
edit4:
VR-Zone sits down with AMD’s embedded boss Scott Aylor to talk about AMD’s push into the world of embedded processing.
http://vr-zone.com/articles/can-amd-make-way-embedded-market/78972.html
Do you think that they will release the low-end a4's along with these or hold off for another few months putting them into market? I can't remember what they did with the Trinity and Richland lines.
Hmm... it seems AMD does want MANTLE on Linux, i seriously did not expected them to do it... this may be GameOver for DX12, as long as AMD hurries to support Linux and open all the documents regarding MANTLE.
Hmm... it seems AMD does want MANTLE on Linux, i seriously did not expected them to do it... this may be GameOver for DX12, as long as AMD hurries to support Linux and open all the documents regarding MANTLE.
Some rumors point out that Valve has delayed Steam machines for MANTLE support. This rumor makes sense for me because Steam machines will compete against PC+Windows+MANTLE and against consoles+low_end_API.
My belief is that AMD is now focusing resources on developing the final spec of MANTLE in collaboration with developers
While I would love to see Mantle on Linux, all I'm seeing here is that the position hasn't changed from 6 months ago. Namely, they're still looking into it, haven't started it yet, don't know when they're going to start and don't have a Linux launch title lined up.
If AMD really wants MANTLE to become a Standard API they seriously need to hurry, if they manage to get some Games with MANTLE on Linux and open all documents before DX12 arrives, then they may have something... otherwise DX12 will eat MANTLE for breakfast.
If AMD really wants MANTLE to become a Standard API they seriously need to hurry, if they manage to get some Games with MANTLE on Linux and open all documents before DX12 arrives, then they may have something... otherwise DX12 will eat MANTLE for breakfast.
Funny how everyone forgets AMD controls maybe 20% of the GPU market? Unless Intel/NVIDIA jump on board, users see no benefit, and the money flows to other APIs instead. AMD can optimize all they want, but if 80% of users see performance boosts only through DX, then which API is going to sell more product?
You also still have the problem where the implementation is tied to GCN, so what happens when AMD moves on to another GPU arch? Now they have the start to make the processing generic, and all those performance gains start to disappear again.
If AMD really wants MANTLE to become a Standard API they seriously need to hurry, if they manage to get some Games with MANTLE on Linux and open all documents before DX12 arrives, then they may have something... otherwise DX12 will eat MANTLE for breakfast.
Patience young padawan, games take time to develop. It will come, it just takes time. The next Civilization title is likely going to be a mantle title with support for linux/mac.
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