truegenius :
Excavator speculation;
Twin Hyper Transport 4.0 busses
Quad Channel DDR4 support
RCM
2,4,6,8 core variants on DT/Mobile
Each core will have a unshared FPU
4 stages of cache, I am assuming this is like Intel and refers to stacking.
As to die size, most speculating 20nm.
hyper transport 4.0 ! that means that Ex-[strike]Girfriend[/strike] will have pcie v3.0 (maybe upto 32 lanes)
i told ya ! they need faster ht for pcie3.0 . [strike]f@#$[/strike] yeah B)
quad channel !
unshared fpu ! means amd is admitting that bd was a crap design
bulldozer = bullcrap (this line may recieve a lot of heat
)
at least exy will represent a good upgrade from my current 1090t
ummm... i think there will be a *clear* separation between APU and what is the traditional approach that will serve the legacy server/high end ( Seamicro server will be heterogeneous APU not CPU ... i suspect).
* Hypertransport will be pervasive, **already is** ( all processors xbar including APUs is a HT switch, meaning in AMD the HT control part is the Integrated northbridge/xbar)... PCIe control will be minimized and more integrated into the Xbar, because HT and PCIe are very compatible at the "physical layer"(matter of fact is only an inversion or lane order), needing only a sideband link for additional control. So every I/O link in AMD can be HT + PCIe at the same time, that is, you can place an HT adapter and a PCIe v3 adapter, in the same physical connector, like : __________(link) ____(sideband) -> PCIe uses only the *link*, HT uses the *link* + *sideband* ( the same physical connector in a row)...
... the magic will be in the integrated controls, and so every AMD's GPGPU adapter could be *link* +*sideband*, that they will fit in any Intel platform by so using only the *link* for PCIe( intel platforms of course will not use "sideband" or HT)... on AMD platforms they will use both and so be a HT link, and so ready for the last phase of HSA with cache coherency(
HT is fundamental for HSA).
* On APU, besides exterior I/O PCIe+HT links, they will have "silicon interposed" 2.5D DRAM (probably GDDR5/6/*), and the bulky exterior DRAM channels could be on the "silicon interposer" not the APU chips, which will have Hypertransport links to this stacked DRAM pile controls(usually the bottom chip on the DRAM stack), DRAM bottom pile control chip which in its turn will have TSV to the 'on interposer' DDR control for exterior DIMM ... this could give a "simulacrum" of continuing with the Moore's Law by going 3D...
* Excavator probably will have at least *3 thread per module ( probably 4)* with separated fetch engines for each thread with an L0,
the same *VERTICAL MULTITHREADING*, and perhaps 5 Heterogeneous cores/clusters on the same CMT scheme; 2 FlexFPU + 2 Integer + 1 Bit Manipulation/encrypt/compress...
So Excavator i suspect will be pretty much BD design where it matters, because one iteration was not very good doesn't mean the design "philosophy" isn't the best ever, for the kind of "
heterogeneous" chips that AMD is pursuing with HSA. And if this HSA has plenty of advantages at many levels, and a guru behind (John Gustafson), i dare to say AMD design is already superior to what intel has (just give them time)... and its BD oriented alright... matter of fact the Jaguar evolution i suspect will be even more modular, which is a requisite if they want to have a "clean" transition to ARM variants, or even mix ARM with x86 on the same chip( intel has none of this "potential" flexibility)...
intel clearly have x86 performance advantage with a huge margin they only need to clock their cpu higher (they have enough tdp room) and no amd can match their cpu performance at that price bracket (example i3@4ghz will trash any amd at current price in same price bracket fir majority of tasks).
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