[citation][nom]blazorthon[/nom]Overclocking isn't introducing instability if you do it properly, it doesn't void the warranty because you'd have to be an idiot to tell AMD or whomever else handles the warranty that you overclocked and they can't know for sure that you did, and I would go as far as saying that the Bulldozer arch is incredible.[/citation]
Overclocking absolutely does introduce instability. It takes the processor outside of the specification and outside of the testing parameters performed by the manufacturer. Taking it outside of the specification introduces additional strain on connected components. Many errors that may occur due to overclocking might not even be noticed because they're corrected automatically.
To make matters worse, the VID that is programmed into the processor at manufacturing time leaves enough voltage headroom to guarantee stability for the duration of the warranty and ideally a long time after. Most overclocking guides have the user find the lowest voltage which is stable for a narrow range of tests. Over time this voltage will become insufficient and at that point it's not a matter of whether or not an error will occur but when. Stability can usually be restored by simply bumping the voltage up but this is a constant game of cat and mouse.
Overclocking is also a complete no-go area for enterprise and business computing which is where Bulldozer is supposed to excel. Opteron's are barely used at all outside of large supercomputers. Right now Intel has a larger share in the server and workstation market than they do in the desktop market.
They could tell if you overclocked the CPU if they really wanted to. Comparing an output frequency from a PLL against a reference frequency burned into the CPU at manufacturing would be a trivial component to design. Committing warranty fraud is frowned upon.
[citation][nom]blazorthon[/nom]It is held back to an extreme by the poor design implementation. A fully optimal design, even without eliminating the resource-sharing, would probably beat Haswell. Yes, it's not perfect, but no arch is. Improved scheduling would help with the apparent bottle-neck greatly (while, as I've previously said, not being a perfect solution unless combined with improved Turbo features) and AMD could simply improve the front-end for that. Also, I call it an apparent bottle-neck because it is more deceptive than you claim.
You seem to not realize that it isn't really a bottle-neck because it is two core's worth of resources that two cores share. Giving a single core two core's worth of resources is bound to improve performance, but is it really a bottle-neck to duplicate resources and share them compared to duplicating them and letting a single core use them? Only in the sense that it can improve performance to do it. Point is that it isn't a hindrance as much as it is a feature to improve things.[/citation]
You're right, it is held back by extremely poor design implementation. If it was so easy to implement properly then why wasn't it implemented properly in the first place?
The execution resources aren't shared between the clusters in each module. Each module has its own front end and back end. If one cluster is disabled, those resources are not made available to the other cluster in the module. The only parts that are shared between the clusters in the module are the L2 cache, L1 instruction cache, and a pair of gimped FPUs. Bulldozer's CMT implementation is not the same as Intel's SMT implementation. With one SMT thread disabled, the entire core's execution resources can still be used because only the front-end is duplicated. With a CMT cluster disabled, the backend resources dedicated to the disabled cluster are lost as well.
[citation][nom]blazorthon[/nom]Beyond that, having the extra die area that goes unused (the disabled cores) when you disable cores on a Bulldozer CPU means that the power consumption and heat generation is reduced, yet still spread accross the chip quite well. This helps with cooling a little because the inactive parts consume almost no power, so they act somewhat like a heat sink for the heat generated by active parts of the CPU.[/citation]
The thermal conductivity of the oxides used in the insulator layer is extremely low. In microprocessors the current flows almost entirely across the surface of the chip so it's in very close proximity to the highly conductive IHS. This is one of the primary reasons why chips are 2 dimensional, current semiconductor technology does not allow for stacked semiconductors to be cooled properly.
Disabling half the cores may significantly reduce heat dissipation but it will only eliminate some of the heat generating components. The rest will still generate heat and this heat will be spread to the IHS where it can dissipate more effectively.
[citation][nom]blazorthon[/nom]Also, since Bulldozer can be worked with to compete with Ivy Bridge exceptionally well and Piledriver seems to be a substantial improvement almost as great as Haswell is expected to be if not as good as Haswell is to be, if AMD really can keep up this cycle, then they can actually surpass Intel if Intel doesn't get into gear beyond this mere tick-tock schedule that is, although pretty effective, not a very quick way to advance in performance if Intel uses paste on each tick[/citation]
Phenom was supposed to beat the QX9650 into the ground. The X4 9600 got demolished by a Q6600. Phenom II's flagship 980 was supposed to beat Sandybridge but could barely keep up with midrange Nehalem processors. Bulldozer can barely keep up with Phenom II in some applications. I'm starting to see a pattern here.
I'm not sure how you can say that "Bulldozer can be worked to compete with Ivy Bridge exceptionally well" when there's a load of benchmarks, both synthetic and real world, showing otherwise. Piledriver is a nice improvement but it's what Bulldozer should have been released as. AMD needs to continuously deliver on gains that are larger than Intel's. If they do not, the gap will continue to widen.
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