67 MTr/mm2 and a 62nm pp (but I can't formally confirm the CPP value as it's behind NDA for now).
http://www.tsmc.com/csr/en/update/innovationAndService/caseStudy/9/index.htmlTSMC set another industry record by launching two separate 7nm FinFET tracks: one optimized for mobile applications, the other for high performance computing applications.
https://www.semiwiki.com/forum/content/7439-tsmc-technologies-mobile-hpc.htmlN7 HPC track provides 13% speed over N7 mobile (7.5T vs 6T), while it has passed the yield and qual tests (SRAM, FEOL, MEOL, BEOL) and MP-ready D0.
And keep this side note in mind.The 7nm HPC platform includes a new design flow being released in June as well as enhanced IP and process optimizations. It drove an ARM A72 to more than 4 GHz. The platform also supports on-chip magnetic inductors to create integrated voltage regulators.
The HPC platform includes high performance transistors that deliver a five percent speed gain over the vanilla 7nm process. Interestingly, TSMC described several techniques driving advances of 4-5 percent across various processes, suggesting the foundry is squeezing out gains wherever it can find them. An automotive variant of the 7nm process will be ready next year.
https://www.eetimes.com/document.asp?doc_id=1331489&page_number=3Finally, TSMC will deliver late this year a machine-learning capability for limited functions on ARM A72 and A73 cores. The capabilities include predicting optimal cell clock-gating to bolster overall chip speeds 50-150 MHz.
The techniques use training models maintained by TSMC using open source algorithms such as Caffe. Designers will be able to create custom scripts they keep privately. Ultimately the service will span more processor types and functions.
For HPC Design Enablement Platform, TSMC further enhanced 7nm and 7nm+_ in process and design solutions to support HPC speed and memory bandwidth requirements. TSMC has demonstrated a 4Ghz ARM core and provided the first Cache Coherence Interconnect for Accelerator (CCIX) silicon demonstration vehicle in 7nm process technology with Xilinx, Arm and Cadence.
http://www.tsmc.com/csr/en/update/innovationAndService/caseStudy/4/index.htmlThrough machine learning, TSMC design enablement platforms produce optimized design constraints and EDA tool scripts, while supporting customers to best utilize the commercial EDA tools from our OIP ecosystem partners.
This collaboration model enables TSMC and our OIP ecosystem partners to focus on our respective strengths, while creating synergy to team up and bring machine learning innovation to the whole design community.
https://www.eetimes.com/document.asp?doc_id=1332293&page_number=2Separately, TSMC reported progress using machine learning to achieve gains such as better route groupings in ARM A72 and A53 cores delivering up to 12% performance gains after synthesis. The foundry will release software scripts at the end of the year that its customers can use as a starting point on their own efforts to eke out more advances.
Cadence is applying machine learning in both verification and its Innovus place-and-route tools, said Anirudh Devgan, who manages two of the company’s divisions. “There are a lot of things that can be done using machine learning,” he said, noting 12% improvements in a 10-nm design.
The A72 sees an even more significant reduction when using a modern FinFET process, such as TSMC’s 16nm FinFET+, where an A72 core stays within a 750mW power envelope at 2.5GHz, according to ARM.
Alternate materials have multiple potential usages in interconnect stacks:
Caps – capping a Cu interconnect line with Co increases the electromigration resistance of the line. TSMC has been doing this since 16nm.
Barrier/seed – when Cu is plated a seed layer is required to plate onto. When Cu was first introduced a TaN barrier with a Cu seed were deposited by physical vapor deposition (PVD). Co (TSMC) and even Ru (Intel) seed layers are being introduced because copper wets better to these films improving fill. Ru seed layers also produce lower resistance plated copper.
Contacts – Co filled contacts have been introduced at 10nm (similar to foundry 7nm) by Intel and 7nm by TSMC. We don’t yet know for sure whether Samsung has Co filled contacts at 7nm but my expectation is they will.
Interconnect – Intel has introduced Co interconnects for metals 0 and 1 at 10nm. The resistance of the lines is higher than it would be for Cu but the lines are short and the via resistance is lower and electromigration is better. Imec has previously stated to me that around 36nm pitch is where Co may begin to offer a benefit and that Intel’s minimum metal pitch. You can see that write up here.
It is hard to determine whether this is a leak or just a placeholder for attention, but it the timing seems quite interesting, considering we are just days away from CES 2019 Keynote where Zen2 are expected to be announced.