Would a shrunken I/O die, a 7nm 8 core chiplet, and 16 gb of HBM2 actually be feasible on an am4 package? That would seemingly be a monstrous gaming CPU. I'm sure this could be pulled off with 3d stacking down the road on a new socket. Probably along with a pretty decent IGPU.
I'm almost certain this arrangement is coming. I arrived at this conclusion about 2 years back when I started looking at the APU side of things. If AMD can provide an APU that provides excellent games at 1440p performance then that would undermine NVIDIA and Intel (If Intel doesn't get it @#$#@ together.) The price to performance would be astounding. That would leave only super high end left. I see NVIDIA holding that crown for at least another 3 years. HOWEVER if 1/2 your raw profits come from mid range, and you are decimated in that area (By AMD's/Intels Super APU's) then your budget for R&D is going to suffer.
What's the biggest sellers? 1060/970/960. All mid range. And an APU that performs as well as a mid range will definitely be cheaper than equivalent separates.
I made lots of predictions of what Navi was going to be starting about 4 years ago. (When Fury was released) Some became true (More ROPs), some are moved to Arcturus. (True Chiplette on the GPU card)
But SRAM & HBM will be on the single chip APU package by next year. It will be a Navi based GCN chiplette similar to Gonzalo.
Arcturus will start breaking up the GPU into shader engines similar to how Zen 2 is broken up. The front end scheduler will handle the tasking out of duties similar to how the io die on Ryzen 3 works. People didn't take me serious when I proposed this because they had SLI/Crossfire stuck in their head. I bet they aren't laughing now.
The IO die on the APU (Picasso) will have an SRAM/E-DRAM area on the IO die just big enough for Draw Calls that are shared with the GPU drawing side of the chip. The GPU buffers will be HBM. HBM is low power and the obvious choice as it requires low trace counts. I originally theorized they would be separate on the same interposer. I'm not sure if chip stacking HBM in this manner is possible. But I could be wrong. If so the chip stack has some very interesting possibilities, especially if tile based culling is improved.
There's still a couple of design issues I'm working out (mainly heat density issues) Expanding an interposer is really not possible at this stage, so it's harder to spread out the heat load. Stacking has it's own issues with heat dissipation. I think I came up with a novel solution to help with the chip stacking heat solution, but I'm keeping my mouth shut.