Although multithreading has long appeared to be a good solution for the mismatch between processor speed and memory bandwidth, the embedded industry has been slow to adopt this technology. This reluctance can be attributed to issues such as the lack of software support, the extra silicon expense, and the use of stopgaps such as DDR memory and larger caches. But the tide may is turning, as witnessed at Microprocessor Forum 2003, as several companies, including Imagination Technologies and MIPS, used this conference as the springboard to launch multithreading products and technologies.
On the surface, the Imagination Technologies META processor is a standard 32-bit architecture that supports both RISC and DSP instructions. The processor has a modular design, typically containing two 32-bit data units, two 32-bit address units, and a control unit. META’s DSP extensions are many of the features found in a full-fledged DSP. The processor implements a system of instruction “template” registers that generates a robust DSP instruction set without requiring an excessively long instruction word.
The most significant feature of the processor is that it maintains a number of separate hardware execution threads. Multithreading allows the META processor to switch contexts in response to rapid real-time events without software overhead. The META processor’s thread-switching ability is based on complex heuristics. The core of a multithreaded system is the hardware scheduler, which determines which threads will be activated. On every cycle, the META scheduler examines the next candidate instruction from each thread and chooses which one to execute. To make this choice, the scheduler considers the availability of more than 50 internal processing resources and a thread prioritization system.
Although MIPS has not yet given out many specific details on actual implementation, the bottom line is a definition of multithreading using a hierarchical approach. At the simplest level, MIPS has developed multithreading semantics that will operate inside an instruction-set architecture that will provide a possibility of expressing to hardware the parallelism of a program in ways that couldn’t be done otherwise. This will allow fine-grain multithreading without a great deal of overhead and anticipate the migration of threads for multithreaded and multiprocessor designs.
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