Question Board Design and Layout of PCIe Skew Requirements

[johnmladenik]

I am designing a board with a PCIe Switch on it. It has a single lanes PCIe Gen 3 Upstream coming in and 5 single lane downstream controlling modules. The On Board PCIe lanes seem straight forward. But what about the upstream from the CPU Board to the Destination board? I found the skew requirements for the PCIe Signal Skew, but it did not specify if those are TX to RX or for the connectors to the PCIe Connector, which we are not using. This is a VPX system not a Standard PCIe system, which uses the PCIe bus for communication between boards with a backplane between boards. So do the skew requirements need to cover across all 3 boards the Source, Backplane and Destination?

 

[Ralston18]

What possible answers (or perhaps solutions) have you considered?

My suggestion is that you post those answers with some supporting information and cited references.

It appears that there are differing VPX architectures/standards - which one are you using?

You will need to provide more details.

 

[johnmladenik]

What possible answers (or perhaps solutions) have you considered?

My suggestion is that you post those answers with some supporting information and cited references.

It appears that there are differing VPX architectures/standards - which one are you using?

You will need to provide more details.

The Board is a 3U boards within the totally new and custom system. The VPX is only mechanical standard not electrical, we are setting those requirements.

The PCIe Skew requirement I found in multiple places indicated a 5mil skew between the +/- pair. It does NOT say if it is between the TX to RX or from the PCIe connector to the RX or TX. And a standard PCIe system typically has two boards, the Processor Board and the Destination, while we have a backplane between the source and detestation boards.

I have done up to 12G differential signals in the past that were not PCIe and used a 2% period for the TX-RX so used 1% on each board and for the 12G signal it had great signal integrity simulation. . But I was hoping to find out what other PCIe Board designed used as their requirements. 5 Mil spacing across 3 boards is quite a task. This is 0.3% of the Period of a Gen 3 PCIe.

We are using Tachyon 100G instead of the common FR4, which gives a better propagation delay and batter for high speed signals then FR4.