Question Board Design and Layout of PCIe Skew Requirements

[johnmladenik]

I am designing a board with a PCIe Switch on it. It has a single lanes PCIe Gen 3 Upstream coming in and 5 single lane downstream controlling modules. The On Board PCIe lanes seem straight forward. But what about the upstream from the CPU Board to the Destination board? I found the skew requirements for the PCIe Signal Skew, but it did not specify if those are TX to RX or for the connectors to the PCIe Connector, which we are not using. This is a VPX system not a Standard PCIe system, which uses the PCIe bus for communication between boards with a backplane between boards. So do the skew requirements need to cover across all 3 boards the Source, Backplane and Destination?

 

[Ralston18]

What possible answers (or perhaps solutions) have you considered?

My suggestion is that you post those answers with some supporting information and cited references.

It appears that there are differing VPX architectures/standards - which one are you using?

You will need to provide more details.

 

[johnmladenik]

What possible answers (or perhaps solutions) have you considered?

My suggestion is that you post those answers with some supporting information and cited references.

It appears that there are differing VPX architectures/standards - which one are you using?

You will need to provide more details.

The Board is a 3U boards within the totally new and custom system. The VPX is only mechanical standard not electrical, we are setting those requirements.

The PCIe Skew requirement I found in multiple places indicated a 5mil skew between the +/- pair. It does NOT say if it is between the TX to RX or from the PCIe connector to the RX or TX. And a standard PCIe system typically has two boards, the Processor Board and the Destination, while we have a backplane between the source and detestation boards.

I have done up to 12G differential signals in the past that were not PCIe and used a 2% period for the TX-RX so used 1% on each board and for the 12G signal it had great signal integrity simulation. . But I was hoping to find out what other PCIe Board designed used as their requirements. 5 Mil spacing across 3 boards is quite a task. This is 0.3% of the Period of a Gen 3 PCIe.

We are using Tachyon 100G instead of the common FR4, which gives a better propagation delay and batter for high speed signals then FR4.

 

[Ralston18]

Thank you.

For the most part, from my perspective, your post and questions are likely among the most complex and demanding questions that I have seen posted.

This is also (full disclosure) now far outside of my comfort zones.

That said, you are now on the right track with respect to posting here.

Continue to post your questions, concerns, problems, and so forth, but be sure to include what you believe to be answers, solutions etc..

There may be other others (EE types ? ) who may later post additional questions, ideas, and suggestions.

Then everyone can benefit and learn.

Including me.

Suggestion:

I noted "The Board is a 3U boards within the totally new and custom system. The VPX is only mechanical standard not electrical, we are setting those requirements."

List those requirements.

 

[johnmladenik]

Thank you.

For the most part, from my perspective, your post and questions are likely among the most complex and demanding questions that I have seen posted.

This is also (full disclosure) now far outside of my comfort zones.

That said, you are now on the right track with respect to posting here.

Continue to post your questions, concerns, problems, and so forth, but be sure to include what you believe to be answers, solutions etc..

There may be other others (EE types ? ) who may later post additional questions, ideas, and suggestions.

Then everyone can benefit and learn.

Including me.

Suggestion:

I noted "The Board is a 3U boards within the totally new and custom system. The VPX is only mechanical standard not electrical, we are setting those requirements."

List those requirements.

Well I am trying to figure out the routing requirements for the PCIe with this question. There is a requirement for 1 PCIe input to a PCIe Switch that drives 5 Different 1553 IO Modules. It would not be of much helped to list out the other requirements like how many analog inputs and outputs, how many Open_28V inputs & outputs ,etc. This question is targeted to any engineer that had designed a custom boards with PCIe control busses on it. They would have to have created constraints/requirements for the layout engineer to be able to lay the boards out, The boards has literally hundreds of individual requirements, none of which are relevant to the knowledge I seek. This information is very specific and not readily available online, which is why I have asked in different forums online. Thee is no better sources than someone who has actually done this design in the past IMHO.

Thanks for you comments, it does help me think things through better than no response at all.

 

[Ralston18]

Interesting...

In the meantime would something like this design application be helpfu?

https://easyeda.com/

(Not a recommendation or endorsement - just a thought.)

Is breadboarding an option?