Celerons rebadged pentiums?

[vlahka]

Hi. I remember a looong while back there were people saying celerons, back then, were rebadged pentium processors that had failed their cache check. ITs hard to find any info on this sort of thing but to the tech people out there is this true and is there any proof on the net to back this up? Thanks.

 

[ChipDeath]

Yes, it was true AFAIK. AMD did the same with Durons. In fact the way they generally work is produce the chips, then test them to see what they can do and bin them accordingly.

If demand was sufficient, then they'd start crippling perfectly good cores. Even doing that is cheaper than having two different core designs.

There's probably plenty of proof, but why do you care? re-enabling the extra cache has been discussed, but I would imagine it's close to impossible to do anyway, and even if you managed it the cache might be defective, and render the whole chip useless.

---
<font color=red>"Life is <i>not</i> like a box of chocolates. It's more like a jar of jalapeńos - what you do today might burn your a<b></b>ss tommorrow."

 

[vlahka]

The reason I'm curious is because I'm having a debate with a friend elsewhere about it. He claims everything I say is just conspiracy theorist trash and theres no proof anywhere. I've known about this for a long time but never actually looked up to see if there was anything to back it up. I believe it, but I needed to find something that actually firmly stated this. Can you give me any help? Would REALLY appreciate it.

 

[Crashman]

Chipdeath's explaination is good and there's no conspiracy in it.

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[Crashman]

By the way, graphics chip companies do the same thing with pipelines, they disable defective pipelines on the more expensive chip to make the cheaper chip.

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[Nights_L]

Then why are people able to re-enable those pipelines and work perfectly? e.g: Wusy's 9800SE ?

 

[thematrixhazuneo]

"Then why are people able to re-enable those pipelines and work perfectly? e.g: Wusy's 9800SE ?"

as stated earlier with the CPU those might not be bad pipes - they just disabled them to make differnt products without changing the core itself.

 

[vlahka]

His post is excellent I agree. But it would be great if there were some articles written somewhere about it. Its a shame theres not one on this site. But still, if anyone knows of antyhing I could use I'd really appreciate it.

 

[Crashman]

Actually there are articles on this very site that say that. You just have to go back around 4 or 5 years to find them.

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[vlahka]

Do you mean actual articals tomshardware wrote stating that the Celerons etc were modified failed pentium chips? Or just info in the forum? I've been having trouble finding info, but possibly I'm using the wrong search key words. Will keep looking.

 

[Crashman]

Yes, I'm certain Tom's Hardware had a couple articles that talked about Coppermine Celerons using Coppermine PIII cores that had cache disabled. They also had articles describing methods used to lock processors, blown bridges, and all that other nice technical stuff that puts me to sleep.

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[Crashman]

He needs proof, so...track down the articles for him, I'm a terrible searcher.

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[endyen]

Here's a little history, that may come to explain things a <A HREF="http://www.tomshardware.com/cpu/20000720/index.html" target="_new">little.</A>
This pretty much says it all.

Almost two years ago, in August 1998, Intel introduced the Celeron processor based on the popular Mendocino core. Its predecessor (Covington) came with the Pentium II Deschutes core, but without using any L2 cache memory. That's why the first generation Celeron processors were rather slow and unsuccessful. On March 29 of this year, Intel introduced two more Celeron processors, clocked at 566 and 600 MHz. These new models are equipped with Intel's latest core (Coppermine) but come with only 128 kBytes of full speed L2 cache (instead of the Pentium III's 256 kBytes), making them really interesting again.

It helps to remember that the "core" at that time was a chip, on a pcb, with the cache mounted seperately.

 

[Guest]

People have to learn how to use google eheh!
I typed "celeron's disabled cache", 5th link is one anandtech article
<A HREF="http://www.anandtech.com/showdoc.html?i=1264&p=2" target="_new">url...</A>
quote from a reputable review site that should make your friend stfu heheh

The Coppermine128 is manufactured by essentially taking a regular Pentium III based on the Coppermine core and disabling half of the L2 cache. This can be verified by looking at the die sizes for both the Coppermine128-based Celerons and the Coppermine Pentium IIIs (they are equal). The reason Intel does this is because there is no guarantee that when they produce a Pentium III with 256KB of L2 cache on-die that all of that 256KB L2 will be functional and fit for sale as a part of a processor. In the event that some of the 256KB L2 fails the required production tests, Intel can simply disable 1/2 of the L2 and re-label the part as a Celeron after changing the clock speed and FSB pins of the CPU.

Straightforward answer to exactly your question!

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[Guest]

Intersting:

Now AMD goes about this problem in an entirely different way. They simply duplicate the number of L2 cache columns and if there is a particular block that fails production tests then AMD can simply disable the entire column. It is because of this that the Thunderbird and Duron are actually two different dies.

Probably not iek this anymore for sempr0n's what do you think?

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[RichPLS]

Ain't it ashame car manufactures do not do this. Would you not love to unlock those extra two disabled cylinders on your 3800 V6!

<pre><font color=red>°¤o,¸¸¸,o¤°`°¤o \\// o¤°`°¤o,¸¸¸,o¤°
And the sign says "You got to have a membership card to get inside" Huh
So I got me a pen and paper And I made up my own little sign</pre><p></font color=red>

 

[vlahka]

You lot are legends. Thanks for the help! I did use google, but I guess my search words weren't spiffy enough.

 

[Guest]

No problemo


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