News Chinese vendor appears to be selling Arrow Lake-S engineering samples for $14

[Admin]

Chinese vendor Xianyu appears to be flipping older Arrow Lake-S engineering samples for $14 each. You can buy one, but you won't have a motherboard to put it in.

Chinese vendor appears to be selling Arrow Lake-S engineering samples for $14 : Read more

 

[DaveLTX]

Isn't arrow lake S going to be made on TSMC N3?
These articles are just mad copy pasting

 

[artk2219]

"which would make Arrow Lake the first INTEL CPU architecture in roughly 20 years to not have two threads per core."

Depending on how you want to look at things, AMD didn't have SMT until at least Bulldozer, unless you take the view that just an integer core counts as a complete core, in which case it would be Ryzen . Personally i think integer cores count since FPU's didnt get integrated until the Pentium era, and we still call everything that came beforehand a single core CPU, and the FPU was the math co-processor, but its murky waters.

 

[Deleted member 2731765]

Isn't arrow lake S going to be made on TSMC N3? These articles are just mad copy pasting

I guess they plan to make only the iGPU tile on TSMC N3 node, but the CPU tile might utilize the 20A node. The iGPU tile will be the same as Meteor Lake, leveraging the Xe-LPG architecture on a TSMC 3nm node.

But yeah, what the article mentions is wrong.

Also, it was confirmed by Intel's CEO Pat that TSMC's N3B process node would be used for the Lunar Lake GPU tiles (Lunar lake lineup which is supposed to be an ultrabook/convertible SoC succeeding Lakefield).

Also, per a recent China Times report, Intel will continue its outsourcing strategy with Arrow Lake and Lunar Lake set to leverage TSMC’s 3nm-class process nodes.

They also mention and confirm that the upcoming 15th Gen "Arrow Lake-S" lineup will utilize the Intel 20A node for the CPU tile, and TSMC’s 3nm (N3) node for the iGPU tile. And, the upgrade from Meteor to Arrow Lake will include a more advanced CPU tile (4->20A), while the iGPU tile remains unchanged.

https://www.chinatimes.com/newspapers/20240223000152-260202?chdtv

 

[Deleted member 2731765]

Arrow Lake might not come with HyperThreading

Speaking of HT, I'm still wondering of Intel's patent which focuses on "Rentable Units" which they filed back last year. The patent calls it as “Instruction Processing Circuit“.

News went silent on this one though, so I'm not sure what to say.

https://www.freepatentsonline.com/y2023/0168898.html

IDK, if you go through the patent carefully, some details are mentioned. Here in the figure below, Intel has highlighted the difference between hyper-threading and Rentable Units on hybrid-core processors, assuming this is still in Intel's consideration for future client CPUs.

The densely shaded areas are P-cores while the lightly shaded ones represent the E-cores.

The Rentable Unit splits the first thread of incoming instructions into two partitions, assigning two different cores to each based on the complexity. There are two threads (1 and 2). The scheduler divides each into three partitions (A, B, C).

The first two partitions of 1 (1A, 1B) are executed on the P-core, while the third (1C) is handed to the E-core. Likewise, the first partition of thread 2 (2A) is processed by the E-core, while the other two (2B, 2C) are executed by the P-core.

So it would appear that the Renting Unit is passing part of the work of the E-Core to the P-Core so that the second one does not find a part of the time stopped.

The patent also mentions that "Rentable Units" will use timers and counters to measure P/E core utilization and send parts of the thread to each core for processing. This inherently requires larger cache sizes, and Arrow Lake is already rumored to have 3 MB of L2 cache per core.

So basically, this appears to be a pseudo-multi-threaded solution that splits the first thread of incoming instructions into two partitions, assigning them to different cores based on complexity more like. 😒

 

[usertests]

The 6P + 16E die seems weird unless it's an Arrow Lake-H mobile one. It's been described as a desktop die months ago but rumors are rumors. Articles from earlier today are omitting that die:

Intel Core Ultra 5 240F "Arrow Lake-S" Desktop CPU Reportedly Based on 8+16 & 6+8 Dies, Aims Entry-Level Segment

Intel's Arrow Lake-S "Core Ultra 200" Desktop CPUs are reportedly going to come in two configurations, an 8+16 and a 6+8 die.

wccftech.com

6+16 slide from January:
https://videocardz.com/newz/leaked-...ores-125w-tdp-full-800-series-chipset-details

 

[Deleted member 2731765]

I guess they can reuse the dies for both the Desktop and Mobile variants, if need be. But in any case, this article just copy/pasted what was previously rumored die configurations.

I"m almost certain the final P+E core config is not yet finalized. Those were just rumors.

The XINO leaker seems new when it comes to rumors, and I haven't heard much from this user before though. And why would only the Ultra 5 240F come in two variants ? What about other SKUs in the lineup ?

Let me dig up some more, as I have quite a few old slides on my old backup hard drive.

 

[DaveLTX]

I guess they plan to make only the iGPU tile on TSMC N3 node, but the CPU tile might utilize the 20A node. The iGPU tile will be the same as Meteor Lake, leveraging the Xe-LPG architecture on a TSMC 3nm node.

But yeah, what the article mentions is wrong.

Also, it was confirmed by Intel's CEO Pat that TSMC's N3B process node would be used for the Lunar Lake GPU tiles (Lunar lake lineup which is supposed to be an ultrabook/convertible SoC succeeding Lakefield).

Also, per a recent China Times report, Intel will continue its outsourcing strategy with Arrow Lake and Lunar Lake set to leverage TSMC’s 3nm-class process nodes.

They also mention and confirm that the upcoming 15th Gen "Arrow Lake-S" lineup will utilize the Intel 20A node for the CPU tile, and TSMC’s 3nm (N3) node for the iGPU tile. And, the upgrade from Meteor to Arrow Lake will include a more advanced CPU tile (4->20A), while the iGPU tile remains unchanged.

https://www.chinatimes.com/newspapers/20240223000152-260202?chdtv

It's a bit of a mess, there's also reports that Arrow Lake lower end would be based on Arrow Lake-H or whatever that only has 6+8 and would actually use 20A while the higher end cores either use TSMC N3 or Intel 3
So it might sound like they have a mess trying to decide what they can *actually* use. Which might very well be the case since Intel manufacturing is a whole mess right now

 

[TechyIT223]

Lol , 14 dollars for a CPU in itself is a huge red flag, regardless of the processor being legit to begin with.

Who knows that sample even works or not. Anyway that new hyper thereading patent looks kinda interesting.

Rentable units ?

 

[DaveLTX]

Lol , 14 dollars for a CPU in itself is a huge red flag, regardless of the processor being legit to begin with.

Who knows that sample even works or not. Anyway that new hyper thereading patent looks kinda interesting.

Rentable units ?

I think its a mechanical sample. How it hasn't been pointed out is beyond me...

 

[TechyIT223]

I think its a mechanical sample. How it hasn't been pointed out is beyond me...

It's a qualification sample. What is mechanical? You mean an engineering production unit?

 

[Deleted member 2731765]

It's a bit of a mess, there's also reports that Arrow Lake lower end would be based on Arrow Lake-H or whatever that only has 6+8 and would actually use 20A while the higher end cores either use TSMC N3 or Intel 3
So it might sound like they have a mess trying to decide what they can *actually* use. Which might very well be the case since Intel manufacturing is a whole mess right now

It might sound like a mess, but like I mentioned above, the core count config is still under finalization, but regarding the process node, at this point many sources, some even official, have confirmed that Arrow Lake/AR-S will indeed use two different process nodes.

The XE-LPG iGPU tile would be made on TSMC N3 node, but the CPU tile might utilize the Intel's own 20A node. The H SKU is the Mobile-based variant of the desktop AR-S -series.

Intel can make the H-series on a different silicon die as well, with a slightly cut-down/altered core config, but nothing is set in stone yet.

 

[Deleted member 2731765]

Here in one of the Intel's official slide, they have also mentioned 20A, 3, and one external node for the upcoming Arrow Lake CPU lineup.

 

[Deleted member 2731765]

Well, since this article is about "Arrow Lake" CPU lineup, let me point this out here itself, since other topics are kind if mixed up right now.

This leak also applies to the upcoming LUNAR LAKE CPU series as well. This is NOT any rumor. But official specs confirmation directly from INTEL.

Anyway, as we know the above two upcoming 'Arrow and 'Lunar Lake' CPU lineup would be sporting new "Lion Cove" P-core, and "Skymont" E-core architectures, a recent Intel presentation targeted at PC OEMs highlighted one important aspect of the "Skymont" E-cores.

The slides are too small and blurry, and the original media post also got deleted, but we have few details.

"Skymont" E-core is said to offer a double-digit IPC gain over the "Crestmont" E-core powering the current "Meteor Lake" processor lineup. Not much surprising though.

This double-digit IPC gain over "Crestmont" is achieved through an improved branch prediction unit, a broader 9-wide Decode unit compared to the 6-wide Decode unit of "Crestmont," and an 8-wide integer ALU, compared to 4 Integer ALU on its predecessor.

There is also a dependency optimization in the out-of-order engine, and deeper queuing across the engine, just to name a few optimizations.

Skymont E core:

9-wide Decode
8 integer ALU
Two-digit IPC