CPU IPC

[AggressorPrime]

This is so far what I believe they are:
K7 = 9
K8 = 11
Pentium 4 / Pentium 4 Xeon / Itanium 2 = 6
Pentium M = 8

I am unsure about the Pentium M and even more unsure about the Itanium 2.

Any valued input is welcomed.

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AMD, Always<P ID="edit"><FONT SIZE=-1><EM>Edited by AggressorPrime on 07/21/04 10:06 AM.</EM></FONT></P>

 

[TheRod]

Humm.... how do you calculate these numbers? IPC can vary depending on the instruction complexity.

And Dothan/Banias should ahve the same or even a bit higher IPC than Athlon 64.

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[AggressorPrime]

I ask people on the AMDForums and also do a Google search.

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[P4Man]

These numbers are meaningless.. they are over-simplified aproximitations of a complex reality at best. IPC varies *GREATLY* between different code (programs). Some instruction can be processed (in theory) in a single cycle, and several of them at once, other will take hundreds of clock cycles to process. Give me any number you want, i'll write you some code that achieves that "IPC" on you processor of choice.

BTW, your numbers don't even look remotely correct for an "average". No way a K8 has nearly twice the IPC of a P4 on average, and no way in hell P4 would equal Itanium in IPC.

Pentium M performs roughly on par with K8 though (clock normalized).

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[AggressorPrime]

Oh, I understand now.
Thank you for your help.

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[Groveling_Wyrm]

I ask people on the AMDForums and also do a Google search.

:frown: :frown: :frown:

Unfortunately, if you would go to an Intel enthusiast forum, you could get numbers that would reciprocate, or be exactly the opposite of those numbers you found. More research would definitely be required before you could come up with a qualified answer.



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[Kanavit]

can't really compare the P-M to A64 IPC. since both chips use different bus architecture. the A64 has no northbridge chip, it uses onboard memory controller. the P-M uses northbridge memory controller. And the bus speeds and memory bandwidth are different.

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[Xeon]

All you need to know is x86 CPU's can't retire more than 3 instructions per clock while the Itanium can do 6.

Xeon

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[phial]

well if thats true, then we cant compare the A64 to the P4 because they have very different platforms as well




oh course you can compare them -_-!
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[imgod2u]

There's maximum sustained and burst issue/retire rate. I'm not too sure about Itanium, but here's the numbers for the K7/K8, Netburst and Banias/Dothan:

Maximum sustained:
1. 3 x86 instructions per clock on the K7/K8
3. 1 x86 instructions per clock or 3 micro-ops per clock (depending on whether decode is neccessary) on Netburst.
4. 3 x86 instructions per clock.

Sustained values rarely match these.

Maximum burst rate in micro-ops issue and retire:
1. 9 micro-ops per clock on K7/K8
2. 4-6 micro-ops per clock (depending on whether you're using the rapid execution engine) on Netburst.
3. 5 micro-ops per clock on Banias/Dothan.

Again, these numbers in no way represent real-world average achieved ILP. Different architectures perform differently depending on instruction sequencing, types of instructions, cache hit rates, memory subsystem performance, etc. etc. etc.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[phial]

that pretty much affirms my 2/3s faster or less per clocks ratio theory about AMD vs P4 based chips

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[Guest]

uh? what does Instruction Per clock has to do with the memory sub-system???

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[phial]

thats what im saying. its irrelivant

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[imgod2u]

Obviously if you can't feed enough instructions/data to the processor, you can't issue/retire/process the maximum number of instructions every clockcycle you could. Hence, the K8 achieves a higher realworld IPC than the K7 even though its core hardware is nearly identical.

Other factors such as data dependencies and (more so on Netburst than on the K7/K8) instruction sequencing/types, can vastly effect your average IPC. Banias/Dothan pretty much showed that it's not the amount of execution hardware you have (as it has 5 issue ports vs 9 on the K7/K8 and 4-6 on Netburst), it's how well you utilize what you have. Modern day code generally does not offer enough dynamic ILP to feed the 9-way, 9-issue K7/K8 engine. It's there to get better burst speeds. Think of ATA-133 vs ATA-100. The HD speed (code ILP) still remains the same.

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[P4Man]

>All you need to know is x86 CPU's can't retire more than 3
>instructions per clock while the Itanium can do 6.

Ahem.. no, that is all you know, period. Knowing what it actually means, might be usefull though.

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[Xeon]

Ahem.. no, that is all you know, period. Knowing what it actually means, might be usefull though.

Aww muffin did you wake up on the wrong side of the globe today... Ya waking up in Europe would make me bitter too.

But the fact remains that x86 or IA-32 can't retire more than 3 instructions per clock and IA-64 can retire 2x more at a whopping 6*rolls eyes*.

So instructions on the fly or decoded instructions per clock which imgod2u just about nailed on the wall aren't very representative of instruction retire and throughput. I really don’t know why you get pissy about it, the information has been posted on here before.

Xeon

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[imgod2u]

But the fact remains that x86 or IA-32 can't retire more than 3 instructions per clock and IA-64 can retire 2x more at a whopping 6*rolls eyes*.

So instructions on the fly or decoded instructions per clock which imgod2u just about nailed on the wall aren't very representative of instruction retire and throughput. I really don’t know why you get pissy about it, the information has been posted on here before.

Erm, to be fair, IA-64 instructions aren't the same as x86 instructions. With complex addressing modes and transcendentals, etc. an x86 instruction probably, on average, equals about 1.5 IA-64 instructions. One of the main ideas behind Netburst was to make the smaller, simpler instructions run really really fast and forget about the rest. That limited developers to what instructions to use (which pissed off quite a few people) but it allowed better performance in the end.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[Xeon]

In the end thought the retire rate is what counts.

Xeon

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[imgod2u]

And retiring an x86 instruction is more significant than retiring an IA-64 instruction on average. What's your point?

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[Xeon]

IPC is my point, you can have 1 trillion instructions in flight but that means jack when only 3 can retire per clock, see my point now?

Xeon

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[Kanavit]

bus speeds are different. the P-m uses only DDR333 and 400fsb. while the A64 uses 1600fsb hypertransport and DDR400. You cannot fairly compare the two. compare the P-M to an Athlon XP 2500+ barton. Memory subsystem architecture is more in common.

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[imgod2u]

bus speeds are different. the P-m uses only DDR333 and 400fsb. while the A64 uses 1600fsb hypertransport and DDR400. You cannot fairly compare the two. compare the P-M to an Athlon XP 2500+ barton. Memory subsystem architecture is more in common.

Not really. Different architectures are designed for different memory subsystems. Banias/Dothan happens to cope very well with low-bandwidth memory subsystems with its huge amount of cache and aggressive prefetching.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[phial]

while the A64 uses 1600fsb hypertransport and DDR400.

its been benchmarked by several sites proving that theres no difference in performance going from 600 to 800mhz hypertransport. and its not really 1600mhz, its 800 with equal bandwidth in each direction



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