Discussion: AMD Ryzen

[simon12]

What do yis make of this over on seekingalpha he works out performance of Zen..
"Zen core would be competitive with things like the i7 2600K, a 2nd generation i7 running at 3.4Ghz base. On single thread performance, this would be below even an i3 4330, a 4th generation i3 running at 3.5Ghz."
http://seekingalpha.com/article/4008322-amd-another-performance-shoe-drops

Aren't current A series CPUs already roughly/nearly competitive with the iX 2XXX series from intel in single core performance? If zen can't compete with Ivy bridge it will have to be cheap to sell many. It could be saved if it works well in laptops as I imagine there are alot more laptops sold than desktops these days.

 

[cdrkf]

What do yis make of this over on seekingalpha he works out performance of Zen..
"Zen core would be competitive with things like the i7 2600K, a 2nd generation i7 running at 3.4Ghz base. On single thread performance, this would be below even an i3 4330, a 4th generation i3 running at 3.5Ghz."
http://seekingalpha.com/article/4008322-amd-another-performance-shoe-drops

Aren't current A series CPUs already roughly/nearly competitive with the iX 2XXX series from intel in single core performance? If zen can't compete with Ivy bridge it will have to be cheap to sell many. It could be saved if it works well in laptops as I imagine there are alot more laptops sold than desktops these days.

It very much depends on *what benchmark* you pick. In that specific metric (Cinebench 2015, single threaded) then AMD are *more than 40% behind Intel*- so that isn't enough to put them directly in contention with Intels latest. There are plenty of other areas where 40% IPC would be enough to put AMD on par with Skylake or even slightly ahead.

My guess is, for IPC, AMD on average should be reasonably close to Haswell. Where they might have an issue is on clock speeds, with Intel being able to push north of 4ghz AMD (at least on the 8 core part) are going to be closer to 3. Hopefully the smaller quad core Zen will be a bit faster in that respect. The thing is though, at over 3ghz, with IPC between Sandy and Haswell and with 8 core / 16 threads, Zen is going to be MUCH faster than anything AMD has ever released before, and critically should be comfortably faster than Intels incumbent quad core mainstream i5 and i7 cpus, and should hopefully nestle in the mix between Intels 6 and 8 core parts in overall performance. If that happens, it's going to put AMD in a *much* stronger position than they are now.

 

[jaymc]

Plus when the new Polaris and then Vega APU's arrive they should really steel a lot of market share in the notebook sector...

That is of coarse as long Nvidia and Intel don't join forces and release an APU of their own... SSSSHHHH!!! don't mention that idea to anyone !!!! 🙂

Only kidding, well not really, whats the chances of that happening... ???
Hopefully Slim.

Jay

 

[juanrga]

Looks to me like your missing the pint Elbert (and about four cores)..... the cores 0, 1, ,2 and 3 on the left are repeated on the right of the annotation...

gmi link #0 is for core complex #0 on the left side i presume and
gmi link #1 is for core complex #1 on the right hand side of the annotation...

and a four core cpu is actually an 8 core with one of the complexes disabled !!!

is that acurate juanrga...?

regards,
jay

Right, it is accurate. Desdrenboy only detailed one complex in the Zeppelin die because the other complex is identical. Chip architect annotated the whole die

AMD will be using with Zen a strategy analogous to the used with Bulldozer/Piledriver

Bulldozer/Piledriver

■ The minimal unit of computation is the module
■ A module are two cores sharing front-end, FPU, L1i and L2 caches
■ All Buldozer CPUs are made with the same die: Orochi. This die has four modules (eight-core) plus L3.
■ Octo core FX-8000 CPUs use the whole die with all modules active. Six-core FX-6000 CPUs use the same die with one module disabled. Quad-core FX-4000 CPUs use the same die with two modules disabled.
■ Higher core-count CPUs are made with multiple dies in a MCM package. For instance the 16-core Opteron are made by joining two eight-core dies.
■ The desktop/mobile APUs are made with a different die. This APU die replaces the L3 cache and two modules of the Orochi die by an iGPU. Therefore the top APU is a quad-core.
■ Dual-core APUs use the same APU die but with two modules disabled. AMD also released Athlon branding CPUs that are APUs with the iGPU disabled.

Zen

■ The minimal unit of computation is the complex
■ A complex are four Zen cores sharing L3 cache
■ All Zen CPUs are made with the same die: Zeppelin. This die has two complexes (eight-core).
■ Octo core Summit Ridge CPUs use the whole die with the two complexes active. Quad-core Summit Ridge CPUs use the same die with one complex disabled. There is no six-core.
■ Higher core-count Zen CPUs are made with multiple dies in a MCM package. For instance the 16-core Opteron are made by joining two eight-core dies. The 32-core Opteron are made by joining four eight-core dies.
■ There is a HPC/server 16-core APU that uses four dies: two Zeppelin dies plus two Vega dies.
■ The desktop/mobile APUs are made with a different die. This APU die replaces one complex of the Zeppelin die by an iGPU. Therefore the top Raven Ridge Zen APU is a quad-core. There is no dual-core Zen APU.
■ AMD could release a different CPU branding from APUs with the iGPU disabled.

 

[juanrga]

I already know 4 core packages had nothing to do with MCM as that is a Zepplin package. IE one Zeppline is a 4 core CPU and two zepplines is 8 core Zen. Your pics all have Zepplin with core 0, 1, 2 , and 3 which is what it is and it takes 2 to make an 8 core. Zepplin is a cluster with each core having its own L1 and L2 cache but all 4 cores share the L3 larger cache. A single silcon can have multiple Zepplin clusters within the physical limits of the process node. MCM is used to splice 2 seperate silicons together and has little to do with Zepplin. IE your Zepplin die count is off.

Wrong.

Snowy Owl and Naples both are not servers. Snowy Owl is a single socket workstation CPU like broadwell-e. Naples is a 2 and 4 socket server CPU.

Snowy Owl is a server chip. The competitor for Broadwell-E is Summit Ridge.

I don't know a single 4P Naples configuration. Only 1P and 2P.

GMI link is an interconnect between complex be they zeppelin or polaris gpu clusters. GMI link is a 100GB wide low latency connection that not only connects complex's but also handles memory coherance and PCI-E among other things.

No. The GMI links connect dies. They don't connect complexes or what you call "clusters".

There is the case where your totally wrong where complex #1 is a polaris GPU cluster of a quad APU. If the GPU cluster is disabled your left with only 1 zeppelin either way.

He is entirely right. He was talking about Zen CPUs, which use the Zeppelin die annotated above. The desktop/mobile Zen APUs will use a different die, not the Zeppelin die. This is the same situation with Piledriver CPUs and APUs. The Piledriver CPUs use the Orochi v3 die, whereas the Piledriver APUs use a different die isn't Orochi.

Na the APU's are set to launch with Zen in Feb but that is a bit away and could be delayed again. Sure they have disabled cores but also GPU's so could be both. Im sure if they can salvage a quad of either it will be done.

No. Only the Summit Ridge CPUs are launched early 2017; and February is not confirmed by AMD, this is a date invented by the media. The Zen APUs for desktop/mobile are scheduled for second half of 2017 and the server/HPC APU is scheduled for 2018.

AMD and GOFLO can catch a break even at skipping a node. TSMC is taking contracts for 7nm early next year with volume production by 2018. This puts GOFLO's 7nm 2 years behind. http://www.digitaltrends.com/computing/tsmc-7nm-2017/

I think AMD should try breaking their contract and let GOFLO float their own ship. Its clearly GOFLO is costing them as Zen could have been out on TSMC's 10nm by now.

Globalfoundries and AMD already are skipping a node. The 10nm Globalfoundries node was canceled and AMD will jump directly from current 14nm to future 7nm.

It is worth to recall that Globalfoundries 7nm is like the TSMC 10nm that will start production this year. This means that Zen+, Vega, and so will be made on an outdated node by about 2019.

AMD and Glofo don't have a contract. They have a mutual wafer agreement (the famous WSA), which was signed when AMD spinoff their manufacturing arms to Glofo. It is worth to remark that AMD had to left its foundry business because it was a disaster due to bad management. Without the mutual wafer agreement Glofo never had accepted the foundries. Yes, Glofo is a disaster, but it is wort to remark it was born from huge mistakes made before by AMD.

The WSA expires in 2025 or so.

 

[jaymc]

Juanrga can I ask you:

Can they break their WSA with glofo ??

I read that they renegotiated their WSA recently so they could use other suppliers.... but doesn't this come at a price (finacial penelty), also is it not only possible if glofo is not able to supply/fill their order, in other words only if glofo cannot meet the demand ?

What would be the repercussions of AMD going to TSMC for instance...?

 

[juanrga]

Apple may ditch intel in favour of new Zen APU....!!
https://www.kitguru.net/lifestyle/apple/matthew-wilson/apple-may-ditch-intel-in-favour-of-amds-zen-cpus-for-future-macbooks/

The source is "Bits and chips", that marvelous source of missinformation...

They claimed October launch for AMD Zen, 16nm TSMC, variable size FPU, >4Ghz clocks, 12 and 20 cores for desktop,...

They also claimed Carrizo was coming with HBM, that dozen of HSA applications were ready to launch after Kaveri, that Bristol Ridge would be a 16CU APU,...

It is not the first time that they claim that Apple will switch to AMD. They did about one year ago

http://www.bitsandchips.it/52-english-news/6183-apple-could-use-custom-x86-soc-made-by-amd

What do yis make of this over on seekingalpha he works out performance of Zen..
"Zen core would be competitive with things like the i7 2600K, a 2nd generation i7 running at 3.4Ghz base. On single thread performance, this would be below even an i3 4330, a 4th generation i3 running at 3.5Ghz."
http://seekingalpha.com/article/4008322-amd-another-performance-shoe-drops

This has been pointed several times in this thread. Take the single thread CB15 score for the Excavator-based Athlon. Multiply it by the 40% IPC gain claimed by AMD and we get Zen score behind Sandy Bridge i7 model at same clocks.

 

[elbert]

Looks to me like your missing the pint Elbert (and about four cores)..... the cores 0, 1, ,2 and 3 on the left are repeated on the right of the annotation...

gmi link #0 is for core complex #0 on the left side i presume and
gmi link #1 is for core complex #1 on the right hand side of the annotation...

and a four core cpu is actually an 8 core with one of the complexes disabled !!!

is that acurate juanrga...?

regards,
jay

Right, it is accurate. Desdrenboy only detailed one complex in the Zeppelin die because the other complex is identical. Chip architect annotated the whole die

AMD will be using with Zen a strategy analogous to the used with Bulldozer/Piledriver

Bulldozer/Piledriver

■ The minimal unit of computation is the module
■ A module are two cores sharing front-end, FPU, L1i and L2 caches
■ All Buldozer CPUs are made with the same die: Orochi. This die has four modules (eight-core) plus L3.
■ Octo core FX-8000 CPUs use the whole die with all modules active. Six-core FX-6000 CPUs use the same die with one module disabled. Quad-core FX-4000 CPUs use the same die with two modules disabled.
■ Higher core-count CPUs are made with multiple dies in a MCM package. For instance the 16-core Opteron are made by joining two eight-core dies.
■ The desktop/mobile APUs are made with a different die. This APU die replaces the L3 cache and two modules of the Orochi die by an iGPU. Therefore the top APU is a quad-core.
■ Dual-core APUs use the same APU die but with two modules disabled. AMD also released Athlon branding CPUs that are APUs with the iGPU disabled.

Zen

■ The minimal unit of computation is the complex
■ A complex are four Zen cores sharing L3 cache
■ All Zen CPUs are made with the same die: Zeppelin. This die has two complexes (eight-core).
■ Octo core Summit Ridge CPUs use the whole die with the two complexes active. Quad-core Summit Ridge CPUs use the same die with one complex disabled. There is no six-core.
■ Higher core-count Zen CPUs are made with multiple dies in a MCM package. For instance the 16-core Opteron are made by joining two eight-core dies. The 32-core Opteron are made by joining four eight-core dies.
■ There is a HPC/server 16-core APU that uses four dies: two Zeppelin dies plus two Vega dies.
■ The desktop/mobile APUs are made with a different die. This APU die replaces one complex of the Zeppelin die by an iGPU. Therefore the top Raven Ridge Zen APU is a quad-core. There is no dual-core Zen APU.
■ AMD could release a different CPU branding from APUs with the iGPU disabled.

Your pics link says Zen with no mention of Zeppelin.

 

[elbert]

I already know 4 core packages had nothing to do with MCM as that is a Zepplin package. IE one Zeppline is a 4 core CPU and two zepplines is 8 core Zen. Your pics all have Zepplin with core 0, 1, 2 , and 3 which is what it is and it takes 2 to make an 8 core. Zepplin is a cluster with each core having its own L1 and L2 cache but all 4 cores share the L3 larger cache. A single silcon can have multiple Zepplin clusters within the physical limits of the process node. MCM is used to splice 2 seperate silicons together and has little to do with Zepplin. IE your Zepplin die count is off.

Wrong.

Snowy Owl and Naples both are not servers. Snowy Owl is a single socket workstation CPU like broadwell-e. Naples is a 2 and 4 socket server CPU.

Snowy Owl is a server chip. The competitor for Broadwell-E is Summit Ridge.

I don't know a single 4P Naples configuration. Only 1P and 2P.

GMI link is an interconnect between complex be they zeppelin or polaris gpu clusters. GMI link is a 100GB wide low latency connection that not only connects complex's but also handles memory coherance and PCI-E among other things.

No. The GMI links connect dies. They don't connect complexes or what you call "clusters".

There is the case where your totally wrong where complex #1 is a polaris GPU cluster of a quad APU. If the GPU cluster is disabled your left with only 1 zeppelin either way.

He is entirely right. He was talking about Zen CPUs, which use the Zeppelin die annotated above. The desktop/mobile Zen APUs will use a different die, not the Zeppelin die. This is the same situation with Piledriver CPUs and APUs. The Piledriver CPUs use the Orochi v3 die, whereas the Piledriver APUs use a different die isn't Orochi.

Na the APU's are set to launch with Zen in Feb but that is a bit away and could be delayed again. Sure they have disabled cores but also GPU's so could be both. Im sure if they can salvage a quad of either it will be done.

No. Only the Summit Ridge CPUs are launched early 2017; and February is not confirmed by AMD, this is a date invented by the media. The Zen APUs for desktop/mobile are scheduled for second half of 2017 and the server/HPC APU is scheduled for 2018.

AMD and GOFLO can catch a break even at skipping a node. TSMC is taking contracts for 7nm early next year with volume production by 2018. This puts GOFLO's 7nm 2 years behind. http://www.digitaltrends.com/computing/tsmc-7nm-2017/

I think AMD should try breaking their contract and let GOFLO float their own ship. Its clearly GOFLO is costing them as Zen could have been out on TSMC's 10nm by now.

Globalfoundries and AMD already are skipping a node. The 10nm Globalfoundries node was canceled and AMD will jump directly from current 14nm to future 7nm.

It is worth to recall that Globalfoundries 7nm is like the TSMC 10nm that will start production this year. This means that Zen+, Vega, and so will be made on an outdated node by about 2019.

AMD and Glofo don't have a contract. They have a mutual wafer agreement (the famous WSA), which was signed when AMD spinoff their manufacturing arms to Glofo. It is worth to remark that AMD had to left its foundry business because it was a disaster due to bad management. Without the mutual wafer agreement Glofo never had accepted the foundries. Yes, Glofo is a disaster, but it is wort to remark it was born from huge mistakes made before by AMD.

The WSA expires in 2025 or so.

I dont know of a 1P Naple the only AMD points to 2P but there has been leaks suggesting 4P.
Summit Ridge is up against Intels dual, quads, hex, and octa. That in no way means its up against Broadwell but only the lower end broadwell at best. Snowy Owl is up against the broadwell-e/p 10, 12, 14, and 16 cores.

Now I like how you reuse my statement they may be delayed to your not confirmed. This really means nothing to anyone to change the possible launch. And no the APU aren't scheduled for anything but like I posted leaks suggests. The leaks still suggest both zen and the APU will launch in Feb. Leaks have only pushed Naple to possible delayed to 2H 2017. Now the agreement between AMD and GOFLO is more like a contract made when GOFLO was spinned off.

 

[juanrga]

Juanrga can I ask you:

Can they break their WSA with glofo ??

I read that they renegotiated their WSA recently so they could use other suppliers.... but doesn't this come at a price (finacial penelty), also is it not only possible if glofo is not able to supply/fill their order, in other words only if glofo cannot meet the demand ?

What would be the repercussions of AMD going to TSMC for instance...?

The WSA agreement expires on 2025 and it includes a minimum of wafers per year that have to be acquired by AMD. If that minimum is fulfilled then AMD has the right to either continue using Glofo for extra products or contract another company.

Precisely the reason why had to move Polaris GPUs from TSMC to Glofo was because they couldn't fulfill the minimum with CPUs/APUs only.

Breaking the agreement implies AMD would have to pay all those waffers will be not ordering to Glofo.

They renegotiated the WSA recently and agreed to pay Glofo a multimillionaire quantity for the the waffers that AMD initially agreed to use, but will be not ordering.

Do you mean full move from Glofo to TSMC? AMD would pay Glofo for the wafers not used. Plus would have to pay TSMC for the wafers used. I.e. AMD would have to pay twice.

Moreover, TSMC has a priority list for accessing the latests nodes. Healty companies as Apple pay a plus for getting priority access. That is the reason why Nvidia has had supply problems with 16nm GPUs.

Those and other points are the reasons why about two years ago I predicted that Zen would be a 14nm product made at Glofo, whereas "Bits and Chips" and other people with 'sources' claimed that Zen was made on 16nm at TSMC.

 

[elbert]

Apple may ditch intel in favour of new Zen APU....!!
https://www.kitguru.net/lifestyle/apple/matthew-wilson/apple-may-ditch-intel-in-favour-of-amds-zen-cpus-for-future-macbooks/

The source is "Bits and chips", that marvelous source of missinformation...

They claimed October launch for AMD Zen, 16nm TSMC, variable size FPU, >4Ghz clocks, 12 and 20 cores for desktop,...

They also claimed Carrizo was coming with HBM, that dozen of HSA applications were ready to launch after Kaveri, that Bristol Ridge would be a 16CU APU,...

It is not the first time that they claim that Apple will switch to AMD. They did about one year ago

http://www.bitsandchips.it/52-english-news/6183-apple-could-use-custom-x86-soc-made-by-amd

What do yis make of this over on seekingalpha he works out performance of Zen..
"Zen core would be competitive with things like the i7 2600K, a 2nd generation i7 running at 3.4Ghz base. On single thread performance, this would be below even an i3 4330, a 4th generation i3 running at 3.5Ghz."
http://seekingalpha.com/article/4008322-amd-another-performance-shoe-drops

This has been pointed several times in this thread. Take the single thread CB15 score for the Excavator-based Athlon. Multiply it by the 40% IPC gain claimed by AMD and we get Zen score behind Sandy Bridge i7 model at same clocks.

We all know the source of missinformation. Leaks are leaks and missinformation can come from all sources. IE just about everyone wrote PCI-E 4.0 will push 300watts though the motherboard. It turned out to be the max including power connectors. Your tell of misinformation is no more than seen on other sites from time to time.

 

[juanrga]

Spoiler

Looks to me like your missing the pint Elbert (and about four cores)..... the cores 0, 1, ,2 and 3 on the left are repeated on the right of the annotation...

gmi link #0 is for core complex #0 on the left side i presume and
gmi link #1 is for core complex #1 on the right hand side of the annotation...

and a four core cpu is actually an 8 core with one of the complexes disabled !!!

is that acurate juanrga...?

regards,
jay

Right, it is accurate. Desdrenboy only detailed one complex in the Zeppelin die because the other complex is identical. Chip architect annotated the whole die

AMD will be using with Zen a strategy analogous to the used with Bulldozer/Piledriver

Bulldozer/Piledriver

■ The minimal unit of computation is the module
■ A module are two cores sharing front-end, FPU, L1i and L2 caches
■ All Buldozer CPUs are made with the same die: Orochi. This die has four modules (eight-core) plus L3.
■ Octo core FX-8000 CPUs use the whole die with all modules active. Six-core FX-6000 CPUs use the same die with one module disabled. Quad-core FX-4000 CPUs use the same die with two modules disabled.
■ Higher core-count CPUs are made with multiple dies in a MCM package. For instance the 16-core Opteron are made by joining two eight-core dies.
■ The desktop/mobile APUs are made with a different die. This APU die replaces the L3 cache and two modules of the Orochi die by an iGPU. Therefore the top APU is a quad-core.
■ Dual-core APUs use the same APU die but with two modules disabled. AMD also released Athlon branding CPUs that are APUs with the iGPU disabled.

Zen

■ The minimal unit of computation is the complex
■ A complex are four Zen cores sharing L3 cache
■ All Zen CPUs are made with the same die: Zeppelin. This die has two complexes (eight-core).
■ Octo core Summit Ridge CPUs use the whole die with the two complexes active. Quad-core Summit Ridge CPUs use the same die with one complex disabled. There is no six-core.
■ Higher core-count Zen CPUs are made with multiple dies in a MCM package. For instance the 16-core Opteron are made by joining two eight-core dies. The 32-core Opteron are made by joining four eight-core dies.
■ There is a HPC/server 16-core APU that uses four dies: two Zeppelin dies plus two Vega dies.
■ The desktop/mobile APUs are made with a different die. This APU die replaces one complex of the Zeppelin die by an iGPU. Therefore the top Raven Ridge Zen APU is a quad-core. There is no dual-core Zen APU.
■ AMD could release a different CPU branding from APUs with the iGPU disabled.

Your pics link says Zen with no mention of Zeppelin.

I think it is rather irrelevant what is in a link name, but if you insist, just check that other link given

https://[...]/Zeppelin_Die_stitched_labelled.png

 

[cdrkf]

Plus when the new Polaris and then Vega APU's arrive they should really steel a lot of market share in the notebook sector...

That is of coarse as long Nvidia and Intel don't join forces and release an APU of their own... SSSSHHHH!!! don't mention that idea to anyone !!!! 🙂

Only kidding, well not really, whats the chances of that happening... ???
Hopefully Slim.

Jay

Intel and nvidia already do make an apu... did you ever wonder how Intel managed to catch up to AMD so quickly with their integrated graphics? Simple, they licence the tech from nvidia, in exchange for a few of their cpu patents which nvidia is using on their arm cpu development.

That licensing deal will finish soon, so there's even been talk of Intel licensing AMD gpu tech in the future, although that to me seems less likely...

 

[elbert]

Spoiler

Looks to me like your missing the pint Elbert (and about four cores)..... the cores 0, 1, ,2 and 3 on the left are repeated on the right of the annotation...

gmi link #0 is for core complex #0 on the left side i presume and
gmi link #1 is for core complex #1 on the right hand side of the annotation...

and a four core cpu is actually an 8 core with one of the complexes disabled !!!

is that acurate juanrga...?

regards,
jay

Right, it is accurate. Desdrenboy only detailed one complex in the Zeppelin die because the other complex is identical. Chip architect annotated the whole die

AMD will be using with Zen a strategy analogous to the used with Bulldozer/Piledriver

Bulldozer/Piledriver

■ The minimal unit of computation is the module
■ A module are two cores sharing front-end, FPU, L1i and L2 caches
■ All Buldozer CPUs are made with the same die: Orochi. This die has four modules (eight-core) plus L3.
■ Octo core FX-8000 CPUs use the whole die with all modules active. Six-core FX-6000 CPUs use the same die with one module disabled. Quad-core FX-4000 CPUs use the same die with two modules disabled.
■ Higher core-count CPUs are made with multiple dies in a MCM package. For instance the 16-core Opteron are made by joining two eight-core dies.
■ The desktop/mobile APUs are made with a different die. This APU die replaces the L3 cache and two modules of the Orochi die by an iGPU. Therefore the top APU is a quad-core.
■ Dual-core APUs use the same APU die but with two modules disabled. AMD also released Athlon branding CPUs that are APUs with the iGPU disabled.

Zen

■ The minimal unit of computation is the complex
■ A complex are four Zen cores sharing L3 cache
■ All Zen CPUs are made with the same die: Zeppelin. This die has two complexes (eight-core).
■ Octo core Summit Ridge CPUs use the whole die with the two complexes active. Quad-core Summit Ridge CPUs use the same die with one complex disabled. There is no six-core.
■ Higher core-count Zen CPUs are made with multiple dies in a MCM package. For instance the 16-core Opteron are made by joining two eight-core dies. The 32-core Opteron are made by joining four eight-core dies.
■ There is a HPC/server 16-core APU that uses four dies: two Zeppelin dies plus two Vega dies.
■ The desktop/mobile APUs are made with a different die. This APU die replaces one complex of the Zeppelin die by an iGPU. Therefore the top Raven Ridge Zen APU is a quad-core. There is no dual-core Zen APU.
■ AMD could release a different CPU branding from APUs with the iGPU disabled.

Your pics link says Zen with no mention of Zeppelin.

I think it is rather irrelevant what is in a link name, but if you insist, just check that other link given

https://[...]/Zeppelin_Die_stitched_labelled.png

Yup that one correctly calls zeppelin with only 4 cores showing.

 

[juanrga]

I dont know of a 1P Naple the only AMD points to 2P but there has been leaks suggesting 4P.
Summit Ridge is up against Intels dual, quads, hex, and octa. That in no way means its up against Broadwell but only the lower end broadwell at best. Snowy Owl is up against the broadwell-e/p 10, 12, 14, and 16 cores.

Now I like how you reuse my statement they may be delayed to your not confirmed. This really means nothing to anyone to change the possible launch. And no the APU aren't scheduled for anything but like I posted leaks suggests. The leaks still suggest both zen and the APU will launch in Feb. Leaks have only pushed Naple to possible delayed to 2H 2017. Now the agreement between AMD and GOFLO is more like a contract made when GOFLO was spinned off.

As stated I don't know any 4P Naples.

The 8-core Summit Ridge is an enthusiast product that targets Broadwell-E. The dual-core and quad-core Skylake and Kabylake mainstream chips are targeted by Raven Ridge. Snowy Owl is a server chip, not a desktop chip as Broadwell-E and Skylake-E series.

Zen CPUs are officially scheduled for early 2017. What I said is that a February launch is not confirmed. "February" is a date invented by the media, not given by AMD nor by any leaks. The Zen APUs for consumers are scheduled for late 2017. Naples is not delayed, it was always a 2H 2017 product.

WSA stands for Wafer Supply Agreement. We don't call it contract, because it is not one.

It is not true that "GOFLO (sic) was spinned off". Glofo was born as a new company when acquired the former AMD foundry group. Precisely that Glofo wasn't part of AMD but a new company external to AMD was the reason why Intel sued AMD for violating the x86 cross-licensing agreement. Both companies closed the disputes with a new agreement that gave Globalfoundries full legal capacity to make x86 chips without a x86 license

http://www.anandtech.com/show/2873

We all know the source of missinformation. Leaks are leaks and missinformation can come from all sources. IE just about everyone wrote PCI-E 4.0 will push 300watts though the motherboard. It turned out to be the max including power connectors. Your tell of misinformation is no more than seen on other sites from time to time.

Honest misinformation can come from the source having access to too early information subject to changes or because the information is misinterpreted by mistake. This is not what is happening here.

Sites are WCCFTECH or bitsandchips are not good sites that make some occasional error. The former is a clickbait site that publishes anything, even one thing and the contrary just to earn money from visits. Those bitsandchips articles are written by a well-known Italian writer that spread hype to manipulate market share. How another reader mentioned in the kitguru site linked above, those 'leaks' about AMD always appear when the AMD stock drops.

Yup that one correctly calls zeppelin with only 4 cores showing.

Everyone is not blind can see eight cores; four in the left hand side of the die and four in the right hand side. Like jaymc already mentioned in a former post you are deliberately ignoring the four cores in the right hand side.

 

[elbert]

I dont know of a 1P Naple the only AMD points to 2P but there has been leaks suggesting 4P.
Summit Ridge is up against Intels dual, quads, hex, and octa. That in no way means its up against Broadwell but only the lower end broadwell at best. Snowy Owl is up against the broadwell-e/p 10, 12, 14, and 16 cores.

Now I like how you reuse my statement they may be delayed to your not confirmed. This really means nothing to anyone to change the possible launch. And no the APU aren't scheduled for anything but like I posted leaks suggests. The leaks still suggest both zen and the APU will launch in Feb. Leaks have only pushed Naple to possible delayed to 2H 2017. Now the agreement between AMD and GOFLO is more like a contract made when GOFLO was spinned off.

As stated I don't know any 4P Naples.

The 8-core Summit Ridge is an enthusiast product that targets Broadwell-E. The dual-core and quad-core Skylake and Kabylake mainstream chips are targeted by Raven Ridge. Snowy Owl is a server chip, not a desktop chip as Broadwell-E and Skylake-E series.

Zen CPUs are officially scheduled for early 2017. What I said is that a February launch is not confirmed. "February" is a date invented by the media, not given by AMD nor by any leaks. The Zen APUs for consumers are scheduled for late 2017. Naples is not delayed, it was always a 2H 2017 product.

WSA stands for Wafer Supply Agreement. We don't call it contract, because it is not one.

It is not true that "GOFLO (sic) was spinned off". Glofo was born as a new company when acquired the former AMD foundry group. Precisely that Glofo wasn't part of AMD but a new company external to AMD was the reason why Intel sued AMD for violating the x86 cross-licensing agreement. Both companies closed the disputes with a new agreement that gave Globalfoundries full legal capacity to make x86 chips without a x86 license

http://www.anandtech.com/show/2873

We all know the source of missinformation. Leaks are leaks and missinformation can come from all sources. IE just about everyone wrote PCI-E 4.0 will push 300watts though the motherboard. It turned out to be the max including power connectors. Your tell of misinformation is no more than seen on other sites from time to time.

Honest misinformation can come from the source having access to too early information subject to changes or because the information is misinterpreted by mistake. This is not what is happening here.

Sites are WCCFTECH or bitsandchips are not good sites that make some occasional error. The former is a clickbait site that publishes anything, even one thing and the contrary just to earn money from visits. Those bitsandchips articles are written by a well-known Italian writer that spread hype to manipulate market share. How another reader mentioned in the kitguru site linked above, those 'leaks' about AMD always appear when the AMD stock drops.

Yup that one correctly calls zeppelin with only 4 cores showing.

Everyone is not blind can see eight cores; four in the left hand side of the die and four in the right hand side. Like jaymc already mentioned in a former post you are deliberately ignoring the four cores in the right hand side.

You are clearly getting ahead of any leaked information with Raven Ridge. Nothing has been offered on the chip which the GPU part could cost overclocking more so than 4 more cores. Basically we can only guess for sure that Raven Ridge can impact Intels dual core. Now Snowy Owl is neather a desktop nor a server chip as its clear with only 16 cores is more of a middle ground which is workstation or high end enthusias. Sure there is some over lap but only naples cpu's will for sure only be servers.

Now your understanding of AMD and GOFLO is funny. The spin off GOFLO had very little to do with the Intel x86 issue. Intel has been in suits with AMD over x86 ever since Intel stopped outsourcing their very old 386 and 486 production. GOFLO was once just AMD's manufacturing arm so what else but a spinoff would it be called?
http://www.pcworld.com/article/160655/article.html

Now it was on page 13 you stated Zen and Naples was alwasys a 2017 product. No delay Now you state its always a 2H 2017 product?

Now anyone not blind can tell you there is only one side printed on the image called Zeppelin. There is nothing in the right side but the statement "core complex #1." That could as easly be a gpu complex but doesn't matter as its not detailed in a diagram. Its not a good ideal to speculation on missing things in a diagram.

 

[jaymc]

No offence Elbert... but if it was a GPU would it not just be one core ? Not four.... it's identical... which leads me to believe it is not a GPU and that it is another 4 zen cores (with identical cache etc). It's more or less a mirror image.

 

[elbert]

No offence Elbert... but if it was a GPU would it not just be one core ? Not four.... it's identical... which leads me to believe it is not a GPU and that it is another 4 zen cores (with identical cache etc). It's more or less a mirror image.

A GPU has many cores with way more than CPU's. Actually the Zeppelin image doesn't show any cores on the right side. Your looking at the image named zen. This is the image named Zeppelin we are talking about.

The Zen summit ridge image is the only one with both detailed. IE even the images suggest Zeppelin is only a single complex.

 

[jaymc]

It's basically identical but reversed... Literally a mirror image. I mean look at the chips closely. Exactly the same order of vertical lines with same distance between them, just reversed.

Both sides look like the diagram of the zeppelin below it, with two extra lines on each side of the annotation just inverted (where the level 3 cache is). You can actually see these two lines in the background in the diagram of the zen pic as well running through the middle of the cores, again where the level 3 cache is, on each side....I think that's because both pictures are of the same thing (the zen pic & the annotation pic that is) !!!

Would it not look different if it were a GPU ?

I mean come on it's a mirror image, it's another 4 zen cores. It even say's so in the zen pic !

Also I don't see how the zen image "suggests" that zeppelin is a single complex as you say it does... When it clearly shows both complex's.. ??

 

[juanrga]

I dont know of a 1P Naple the only AMD points to 2P but there has been leaks suggesting 4P.
Summit Ridge is up against Intels dual, quads, hex, and octa. That in no way means its up against Broadwell but only the lower end broadwell at best. Snowy Owl is up against the broadwell-e/p 10, 12, 14, and 16 cores.

Now I like how you reuse my statement they may be delayed to your not confirmed. This really means nothing to anyone to change the possible launch. And no the APU aren't scheduled for anything but like I posted leaks suggests. The leaks still suggest both zen and the APU will launch in Feb. Leaks have only pushed Naple to possible delayed to 2H 2017. Now the agreement between AMD and GOFLO is more like a contract made when GOFLO was spinned off.

As stated I don't know any 4P Naples.

The 8-core Summit Ridge is an enthusiast product that targets Broadwell-E. The dual-core and quad-core Skylake and Kabylake mainstream chips are targeted by Raven Ridge. Snowy Owl is a server chip, not a desktop chip as Broadwell-E and Skylake-E series.

Zen CPUs are officially scheduled for early 2017. What I said is that a February launch is not confirmed. "February" is a date invented by the media, not given by AMD nor by any leaks. The Zen APUs for consumers are scheduled for late 2017. Naples is not delayed, it was always a 2H 2017 product.

WSA stands for Wafer Supply Agreement. We don't call it contract, because it is not one.

It is not true that "GOFLO (sic) was spinned off". Glofo was born as a new company when acquired the former AMD foundry group. Precisely that Glofo wasn't part of AMD but a new company external to AMD was the reason why Intel sued AMD for violating the x86 cross-licensing agreement. Both companies closed the disputes with a new agreement that gave Globalfoundries full legal capacity to make x86 chips without a x86 license

http://www.anandtech.com/show/2873

We all know the source of missinformation. Leaks are leaks and missinformation can come from all sources. IE just about everyone wrote PCI-E 4.0 will push 300watts though the motherboard. It turned out to be the max including power connectors. Your tell of misinformation is no more than seen on other sites from time to time.

Honest misinformation can come from the source having access to too early information subject to changes or because the information is misinterpreted by mistake. This is not what is happening here.

Sites are WCCFTECH or bitsandchips are not good sites that make some occasional error. The former is a clickbait site that publishes anything, even one thing and the contrary just to earn money from visits. Those bitsandchips articles are written by a well-known Italian writer that spread hype to manipulate market share. How another reader mentioned in the kitguru site linked above, those 'leaks' about AMD always appear when the AMD stock drops.

Yup that one correctly calls zeppelin with only 4 cores showing.

Everyone is not blind can see eight cores; four in the left hand side of the die and four in the right hand side. Like jaymc already mentioned in a former post you are deliberately ignoring the four cores in the right hand side.

You are clearly getting ahead of any leaked information with Raven Ridge. Nothing has been offered on the chip which the GPU part could cost overclocking more so than 4 more cores. Basically we can only guess for sure that Raven Ridge can impact Intels dual core. Now Snowy Owl is neather a desktop nor a server chip as its clear with only 16 cores is more of a middle ground which is workstation or high end enthusias. Sure there is some over lap but only naples cpu's will for sure only be servers.

Now your understanding of AMD and GOFLO is funny. The spin off GOFLO had very little to do with the Intel x86 issue. Intel has been in suits with AMD over x86 ever since Intel stopped outsourcing their very old 386 and 486 production. GOFLO was once just AMD's manufacturing arm so what else but a spinoff would it be called?
http://www.pcworld.com/article/160655/article.html

Now it was on page 13 you stated Zen and Naples was alwasys a 2017 product. No delay Now you state its always a 2H 2017 product?

Now anyone not blind can tell you there is only one side printed on the image called Zeppelin. There is nothing in the right side but the statement "core complex #1." That could as easly be a gpu complex but doesn't matter as its not detailed in a diagram. Its not a good ideal to speculation on missing things in a diagram.

This is all wrong and corrected before. Moreover, the link you provide once again contradicts what you say.

 

[-Fran-]

From what it's worth, the images you posted elbert do make it appear like they are 2 clusters with 4cores each (as in, a full CPU, not and APU).

Cheers!

 

[juanrga]

It's basically identical but reversed... Literally a mirror image. I mean look at the chips closely. Exactly the same order of vertical lines with same distance between them, just reversed.

Both sides look like the diagram of the zeppelin below it, with two extra lines on each side of the annotation just inverted (where the level 3 cache is). You can actually see these two lines in the background in the diagram of the zen pic as well running through the middle of the cores, again where the level 3 cache is, on each side....I think that's because both pictures are of the same thing (the zen pic & the annotation pic that is) !!!

Would it not look different if it were a GPU ?

I mean come on it's a mirror image, it's another 4 zen cores. It even say's so in the zen pic !

Also I don't see how the zen image "suggests" that zeppelin is a single complex as you say it does... When it clearly shows both complex's.. ??

He is plain wrong. As you correctly mention, both are the same image of a Zeppelin die. Both Desdrenboy and chip-architect got the same original image from a forum post from me. The only difference is that Desdrenboy only detailed the substructures of the complex #0 because the complex #1 is identical (one can see both structures are identical with four cores and the L2 and L3 caches on the complex #0, and the same four cores and the L2 and L3 caches on the complex #1). Chip architect annotated both complexes and rotated the image by 90º compared to Desdrenboy.

This is the original image both used for analysis. It is a wafer with Zeppelin dies

Desdrenboy and chip-architect rotated the original image, cut off one of the 8-core dies and then analyzed the structure in it: Zen cores, caches, memory controllers, GMI links,...

 

[-Fran-]

He is plain wrong. As you correctly mention, both are the same image of a Summit Ridge CPU. Both Desdrenboy and chip-architect got the same original image from a forum post from me. The only difference is that Desdrenboy only detailed the substructures of the complex #0 because the complex #1 is identical (one can see both structures are identical with four cores and the L2 and L3 caches on the complex #0, and the same four cores and the L2 and L3 caches on the complex #1). Chip architect annotated both complexes and rotated the image by 90º compared to Desdrenboy.

This is the original image both used for analysis. It is a wafer with Zeppelin dies

Desdrenboy and chip-architect rotated the original image, cut off one of the 8-core dies and then analyzed the structure in it: Zen cores, caches, memory controllers, GMI links,...

Is that image from WTFBBQTech originally? And it was used for the leaked information you're pushing forward?

Oh, the irony if it is.

Cheers!

 

[juanrga]

He is plain wrong. As you correctly mention, both are the same image of a Zeppelin die. Both Desdrenboy and chip-architect got the same original image from a forum post from me. The only difference is that Desdrenboy only detailed the substructures of the complex #0 because the complex #1 is identical (one can see both structures are identical with four cores and the L2 and L3 caches on the complex #0, and the same four cores and the L2 and L3 caches on the complex #1). Chip architect annotated both complexes and rotated the image by 90º compared to Desdrenboy.

This is the original image both used for analysis. It is a wafer with Zeppelin dies

Desdrenboy and chip-architect rotated the original image, cut off one of the 8-core dies and then analyzed the structure in it: Zen cores, caches, memory controllers, GMI links,...

Is that image from WTFBBQTech originally? And it was used for the leaked information you're pushing forward?

Oh, the irony if it is.

No. "WTFBBQTech" doesn't have anything original. I posted a slide with that image on a SA forum about Zen, then Thomas Ryan noticed the die in the slide and asked me what was that die, because it didn't look as any known die. I said him it was the die for Zen CPUs. Then four posters, including me helped him to analyze the structures on that die. And finally Ryan published a news article on SA about all this, with other sites immediately making eco. WCCFTECH got the image from us and add their logo.

As mentioned multiple times, the only reason why I link to WCCFTECH images is because I want them to waste server bandwidth, since they stole content from other sites and forums.

 

[gamerk316]

Aren't current A series CPUs already roughly/nearly competitive with the iX 2XXX series from intel in single core performance? If zen can't compete with Ivy bridge it will have to be cheap to sell many. It could be saved if it works well in laptops as I imagine there are alot more laptops sold than desktops these days.

Do remember that the 2600k in particular still performs exactly the same in most games as the newest Skylake CPUs, due to the GPU being a bottleneck. At least for gaming, AMD doesn't need much extra performance to hit the same performance wall as Intel. I have NO doubt that at least for gaming, Zen will be fast enough to hit that GPU bottleneck. Intel will still be faster (still predicting IB/HW performance), but the majority of people won't notice, since the people who will purchase Zen will tend to do so for gaming purposes.

If for some reason AMD can't reach that level of performance, then frankly, they deserve to go bankrupt.