I'm using the AMD fx55 today. So thisline caused the 'first' introduction on L3 cache into Intel processors?[/quote]
No. As far as I can tell, the first Intel CPU with L3 cache was the original "Merced" itanium. The next one was the Xeon MP "Foster", which was the Xeon equivalent of the P4 Willamette, but with 512 KB-1 MB of L3 cache added. Intel has been putting L3 cache on every Itanium since its inception and sometimes puts L3 cache on Xeon MPs:
- Foster MP (P4 Willamette equivalent): 512KB or 1 MB L3
- Gallatin (P4 Northwood equivalent): 1, 2, or 4 MB L3
- Cranford (P4 Prescott equivalent): no L3
- Potomac (P4 Prescott equivalent): 4 or 8 MB L3
- Paxville MP (Pentium D Smithfield equivalent): no L3
- Tulsa (Pentium D Presler equivalent): 4, 8, or 16 MB L3
- Tigerton (Core 2 Conroe/Kentsfield equivalent): no L3
- Dunnington (Core 2 Yorkfield equivalent): 8, 12, or 16 MB L3
- Nehalem-EX: 12, 18, or 24 MB L3
The only x86 Intel chips designed for two-socket or single-socket operation that had any L3 cache were the Gallatin and the current Nehalem/Westmere units. All future Xeons will likely have L3 cache since the L3 cache is used in all of Intel's CPUs with more than two cores per die, rather than just in 4P+ systems to help lessen FSB traffic.
Interesting fact: the first x86 CPU with L3 cache is the AMD K6-III when placed in a Super 7 motherboard with cache SRAMs. The motherboard cache would have been the L2 cache on K6s and K6-2s that lack any on-die L2 cache, but the L2 cache-equipped K6-III used the motherboard cache as an L3 cache. AMD would not make another CPU that used L3 cache until the Barcelona Opteron 8 years later.
Can you tell me what data is involved specifically being procesed with L3 cache? Data that would otherwise not be eligible to be held by the CPU for processing with L2 cache?
Basically, yes. It also is used to store information prefetched from memory for use by the various CPUs and likely to store some data passed between CPU cores as well.