When planar transistor scaling stopped, the nomenclature was meant to continue by way of equivalency in transistor density increases. Traditionally the half-pitch of the planar transistor was scaled down to sqrt(2) (that’s ≈0.71x) of what it was in the previous node and that would result in a 2x increase in transistor density in the new node. So when the move was made from planar transistors to 3D FinFETs etc, a new node was meant to be defined by a 2x increase in transistor density. The node would be named after the half-pitch of a hypothetical planar transistor that would achieve that 2x increase in density – that is with a half-pitch shrank to 0.71x. Intel going from 14nm to 10nm represents exactly this philosophy. Intel actually aimed and achieved an even larger increase than just 2x – the original aim was 2.7x – and what was actually achieved, even after the relaxations to improve yields, is still well above 2x. Calling it 9nm would be more accurate than 10nm but anyway.
I don’t know how Intel will end up advertising their nodes but they are not the ones who rendered the nanoscale nomenclature useless. That feat goes to Samsung, Global Foundries and TSMC and their shameless marketing shenanigans. For example TSMC and Global Foundries called their 16nm intranode improvements “12nm”. Using the abovementioned equivalency philosophy a true 12nm process would have represented a 1.78x increase in transistor density. But what the foundries achieved was a mere 5% increase that Intel would not even use a plus sign to represent let alone call it a new name to appear as a new node. All while the 16nm name was not accurate to begin with. On Intel’s scale it would be called 18nm. Anyway, TSMC did move to a new node that was indeed a 2x increase over their ‘16nm’ (which is actually 18nm) node. They called it ‘10nm’. Using Intel’s scale that would land to 0.71x18nm=12.8nm. Since TSMC was calling their previous node ‘16nm’ it could be called “11.4nm”. But then factoring the intranode improvements (called “12nm”) they called it “10nm”. Then there was the move to “7nm”. That according to the equivalency philosophy should have represented another 2x increase in transistor density. But it only achieved 1.6x. Not bad but still not 2x. Even accepting their “10nm” as an accurate name, the new node, given the 1.6x achieved density, should have been named “8nm”. Going by Intel’s scale it would be 0.79x12.78=10nm. The intranode improvements with N7P achieved a further 18% increase in density putting it at 9.2nm on Intel’s scale, ever so slightly behind Intel’s 10nm which is actually around 9nm. Thus there is pretty much complete parity between TSMC's 7nm+ and Intel's 10nm.
Mod Edit - Keep it polite
For those that keep spouting the theoretical crap about the new density measurement are failing to understand the process of PCB design and manufacture, and how multilayer circuits work. Now for the Uninitiated and those that don't understand ASIC design, take a look at Intel's proposed 3D Transistor design that was meant to be the design methodology for their 10nm node. Intel had a great idea but have failed to implement it in any great degree at their 10nm node, and have chosen not to upgrade all its Lithography to the 10nm process, because the Yields from the starts are poor and unpredictable.
Take a look at this
https://hexus.net/tech/news/industry/147520-samsung-3nm-nanosheet-transistor-advantages-described/
Intel Newsroom home page
newsroom.intel.com
https://semiaccurate.com/2011/08/18/intel-moves-transistors-from-2d-to-3d-and-more
Intel Chose to use the Stacked Nanosheet FET design that allows for a 3 transistor per unit area (and it works for 14nm, but not 10nm) of the equivalent Planar tech where as classical design used the Standard FinFET or the dual Fin Fet design that TSMC uses that has a 2 FET per unit area compared to Intel's 3 per unit area. The advantage about the 2 FET design structure is the planar connections are Perpendicular, allowing for the connections to be more simply added without binding to other nano-wires that causes fails in the Lithographic metal layering process. (note that one fail causes a failed core, leading to failure rates). Intel's stacked FinFET design layers 3 on top of each other, not only meaning that the Gate transistor control is difficult to master, but the tech is infinitely more complex that the density that TSMC has. But choosing a simpler Nano tech means lesser density, but far greater success in yields an more easily shrunk size for the transistor. The Transistor size is correct 7nm for TSMC as it is for Intel, the only thing that makes it difficult is the tri-stack and Intel cannot master the 10nm node because even though they have some success with the node, they also have a massive failure rate due to the difficulty of working with the layering and connecting process of all 3 transistors without binding some of the nano wires together.
Enter the Dragon; Samsung has design a process called the GATE ALL AROUND design method, and Samsung has nailed the design using Nanosheets of Germanium-silicon composites for the gate connection allowing it to create the 3D design of Tri-layer design all the way down to 3nm. So TSMC you can mock, but Samsung is Thrashing everyone here with Lithographic size.
Intel took a risk and decided to use Crystalline metals (cobalt) to get around its yield issues (and we will see if that works) but it is still now 3-5 years behind Samsung. who already have a working prototype and are also being transparent in how they are accomplishing what Intel has struggled to perfect since 2011. The solution is not prefect, as germanium has leakage problems in reverse BIAS with transistors, but has a smaller gate control voltage of half of silicone's forward bias voltage. So in Idle, I predict that it will drain more power (unless they have a control circuit that turns off segments of the PCB when not in use, which is mainstream now).
Now on the second point, Intel's density per unit area is compromises of poor thermal design (allowing transistors to be closer that they should be to other transistors) which raises temperature above thermal norms. Chips that go above 70 degrees risk unsoldering themselves over time, and Intel clearly doesn't care about this. it is risking high warrantee failures and compensation, just to stay in the game. Yes it can afford it, but personally, I see a massive desperate move here. Data centers and other large scale computer use based companies would be fools to go with the new Intel chips. it would cost them massively in complex board purchases with aftermarket coolers/throttled processors and massive electricity cost rises per day.
AMD takes the TSMC, approach which is safe, keep the design traditional and keep yields high, and now AMD can keep up with Intel in many IPC benchmarks, while having lower clocks and lower power consumption. It is a win for AMD as they can keep up with half the power, and will sell better to data centres now that look to save money on running costs.
Please stop coming out with uninformed opinions, Intel are desperate , deal with it!
Facebook
Twitter
Instagram