News Intel’s turnaround plan hinges on this one chip family – Clearwater Forest pictured, Intel’s first 18A chip slated for high-volume manufacturing.

[thestryker]

That's different than their research nodes, which it sounds like you're trying to claim it was. For instance, Intel made a research node to test out backside power delivery, based on Intel 3, and used it to fab a Crestmont core. That weird hybrid node was never previously announced. It didn't show up on their roadmap and they only mentioned it after the fact.

*Intel 4

just like I'm not sure about backside power delivery.

I think BSPDN is going to be a pretty clear advantage, but since everyone implementing it has indicated it's going to be optional says to me it won't be universal and will likely be expensive.

 

[bit_user]

I think BSPDN is going to be a pretty clear advantage,

I didn't say it wouldn't be an advantage. I just meant that maybe a combination of other improvements could yield a comparable node which lacks it. That's what I meant by not being an unassailable advantage.

My full quote was:

In my mind, it's not a given that high-NA will confer an unassailable advantage, just like I'm not sure about backside power delivery.

 

[bit_user]

BTW, I don't want to sound unduly negative. I'm not ruling out the possibility that Intel really will take the lead with 18A and hold it with 14A.

All I'm saying is that I'm just not very confident that will happen and that those nodes won't be affected by any sorts of delays or other problems.

 

[thestryker]

I didn't say it wouldn't be an advantage. I just meant that maybe a combination of other improvements could yield a comparable node which lacks it.

This doesn't seem likely at all if referring to the same class of node due to the rather large shift in design. The biggest question I have regarding BSPDN is what class of chip can leverage it versus not or if it's simply a cost thing. Ex: would it make a notable difference for larger die which has to maximize power per core or is it more of a power density type advantage where high power/clocking cores would get the most benefit.

That's what I meant by not being an unassailable advantage.

My full quote was:

​

In my mind, it's not a given that high-NA will confer an unassailable advantage, just like I'm not sure about backside power delivery.

Fair! I took it as two statements because of the way it was worded. I think you're absolutely right about High-NA as it seems like it certainly has potential, but one of the biggest universal advantages it was originally going to have is wafer processing speed. Perhaps the timing was off due to the delays, but the most recent EUV machines are now much closer to that speed than prior models.

 

[bit_user]

The biggest question I have regarding BSPDN is what class of chip can leverage it versus not or if it's simply a cost thing. Ex: would it make a notable difference for larger die which has to maximize power per core or is it more of a power density type advantage where high power/clocking cores would get the most benefit.

Based on what I've read about it, the main way it increases density is just by moving the large power distribution wires out of the layers with most of the logic and signal wires. I think its befenefits should be applicable to most chips, but you might have a point about ultra low-power designs.