News Intel Announces Delay to 7nm Processors, Now One Year Behind Expectations

[Ncogneto]

Just because LTT agrees with you doesn't make it right. It's an opinion and nothing else. In spite of fancy graphs, he has absolutely zero proof. Being an influencer, it makes sense that Linus would tend to view things through that lens.

Apple didn't become a trillion-dollar company by selling hardware at reasonable prices, to its mac addicts. Like any good drug dealer, Apple knows they're hooked on its product. Furthermore, mac users almost seem to enjoy complaining about how much money Apple is squeezing out of them. Once Apple figured this out, they realized it was like a license to print money.

And likewise, just because you disagree, doesn't make it wrong. As a matter of fact, I can offer quite a bit more proof to back up my view than you can to back up yours.

1. Apple has done this in the past, and remains hugely successful
2. Every review/ Tech site article that spoke about the wheels also spoke about the Apple computer they were for. Some actually went into great detail on said computer, at no cost to apple.
3. We are still talking about it now

Game........Set.........Match

ps. Linus has a great bit more knowledge on how sales/marketing works then you or I ever will.

 

[InvalidError]

The whole concept of current ISA's is based on a memory model that basically pretends cache doesn't exist, yet is deeply dependent on it for decent performance. That's got to change, since cache makes life easy for software, by placing nearly all the burden on hardware - very energy-intensive.

I don't see how this could possibly change in any meaningful manner: even if you gave software the ability to control cache lines, software would still need to compute load/store addresses ahead of load/store instructions needing them and once the CPU's scheduler is already prioritizing load/store dependencies to hopefully have them ready before anything might stall on it, it makes no difference whether the operation sequence got triggered by an explicit cache line manipulation instruction or an implicit one within a load/store instruction.

I'm not seeing where the potential energy saving here. I'd actually be very wary of putting cache line control into software's hands since I'd imagine this being a huge can of worms for timing-based side-channel attacks.

 

[bit_user]

And likewise, just because you disagree, doesn't make it wrong.

Sure, but what is wrong is insulting another user because they disagree.

Furthermore, I bristle at the idea that we shouldn't criticize or even ridicule Apple for that move, even if it's exactly as Linus believes. If Apple wants the supposed benefits of this publicity, they should also have to live with the down sides.

As a matter of fact, I can offer quite a bit more proof to back up my view than you can to back up yours.

1. Apple has done this in the past, and remains hugely successful
2. Every review/ Tech site article that spoke about the wheels also spoke about the Apple computer they were for. Some actually went into great detail on said computer, at no cost to apple.
3. We are still talking about it now

Game........Set.........Match

ps. Linus has a great bit more knowledge on how sales/marketing works then you or I ever will.

None of that is proof. You're basically just repeating Linus' points. Proof would be an Apple marketing exec spilling the beans, or a credible leak of an internal email.

And we're not talking about it in favorable terms. Nobody here is going to buy a Mac, because of this thread. Like I said, people who are realistically in the market for a Power Mac already know about them, making further advertising (whether paid or not) basically pointless.

 

[Ncogneto]

Sure, but what is wrong is insulting another user because they disagree.

Furthermore, I bristle at the idea that we shouldn't criticize or even ridicule Apple for that move, even if it's exactly as Linus believes. If Apple wants the supposed benefits of this publicity, they should also have to live with the down sides.


None of that is proof. You're basically just repeating Linus' points. Proof would be an Apple marketing exec spilling the beans, or a credible leak of an internal email.

And we're not talking about it in favorable terms. Nobody here is going to buy a Mac, because of this thread. Like I said, people who are realistically in the market for a Power Mac already know about them, making further advertising (whether paid or not) basically pointless.

You might want to revisit the insult. Given the context (user was far more insulting to Apple, than I to him) it was fair game.

The proof is they got free publicity. Not sure why that is so hard to understand (oops, is that an insult too?).

Your only counter argument is that I can't prove that was their intent. Seriously? They are, after all $700 computer wheels. You seriously think that they weren't aware of the fall-out? You don't think there multi-million dollar marketing team had a plan?

come on man!

I suppose they also planned on selling a lot of thier 14k gold apple watches too.

 

[bit_user]

I don't see how this could possibly change in any meaningful manner:

I'm pointing out a weakness more than proposing a solution. However, one use case that's easily solvable is how cache is used to hold temporary variables. That could be replaced by having on-chip scratch pad memory that's largely software-managed. GPUs do this, for instance.

I'm not seeing where the potential energy saving here.

I can name at least 3 places:

1. Having to perform n-way lookup for every memory transaction, at each level of the cache hierarchy.
2. Transacting in whole cachelines, when maybe the software only wants a couple bytes of it (see also: write-miss penalty).
3. Cache coherency overhead.

I'd actually be very wary of putting cache line control into software's hands

First, that's not really what I was proposing.

Second, it's already increasingly going there. Just focusing on x86:

• The 80486 introduced the following instructions:
  • INVD — Invalidate Internal Caches
  • WBINVD — Write Back and Invalidate Cache
• The Pentium 3 introduced:
  • MOVNT* — Store <vector> Using Non-Temporal Hint (i.e. cache bypass)
• The Pentium 4 introduced:
  • CLFLUSH — Flush Cache Line
• Athlon & Nehalem introduced:
  • PREFETCHh — Prefetch Data Into Caches
  • PREFETCHW — Prefetch Data into Caches in Anticipation of a Write
• Skylake introduced:
  • CLFLUSHOPT — Flush Cache Line Optimized
• Tremont introduced:
  • CLWB — Force cache line write-back without flush
  • CLDEMOTE — Cache line demote instruction

 

[bit_user]

The proof is they got free publicity.

That is not proof. Confusing it with proof is exactly the sort of fuzzy thinking that has so many people believing conspiracy theories, these days.

Your only counter argument is that I can't prove that was their intent. Seriously?

It's not a counter-argument, it's a statement of fact. And I didn't say you "can't prove", only that you haven't provided proof.

You are ascribing a motive. You need evidence that it was indeed their motive. You have not provided it.

I'm not going to continue debating this, because it's silly, off-topic, and amounts to nothing more than an irreconcilable difference of opinions. I have already stated my opinion and have nothing more to say.

 

[Chung Leong]

I think the next level of CPU performance and efficiency will need a much deeper re-think. The whole concept of current ISA's is based on a memory model that basically pretends cache doesn't exist, yet is deeply dependent on it for decent performance. That's got to change, since cache makes life easy for software, by placing nearly all the burden on hardware - very energy-intensive.

The voice of Itanium from beyond the grave! If we can't even rely on compilers to extract parallelism, what's the chance that they can properly manage CPU caches?

 

[InvalidError]

The voice of Itanium from beyond the grave! If we can't even rely on compilers to extract parallelism, what's the chance that they can properly manage CPU caches?

I thought of Itanium too. If letting the compiler drop optimization hints and neatly packing instructions failed to yield the expected benefits, it seems unlikely that offloading other on-the-fly optimizations from the CPU scheduler is going to help much. At the end of the day, only the CPU cores possess the information required to make optimal clock-by-clock decisions based on current machine state in an increasingly unpredictable environment.

The biggest problem with baking optimizations into the code or compiler is that the compiler/code cannot account for architectural changes that make formerly optimal code no longer optimal. Letting the CPU make those calls gives a whole lot more design flexibility from code to silicon.

 

[Chung Leong]

I thought of Itanium too. If letting the compiler drop optimization hints and neatly packing instructions failed to yield the expected benefits, it seems unlikely that offloading other on-the-fly optimizations from the CPU scheduler is going to help much. At the end of the day, only the CPU cores possess the information required to make optimal clock-by-clock decisions based on current machine state in an increasingly unpredictable environment.

Context switches would be impossibly expensive too, since we'd need to push/pop all cache levels.

I think even register allocation could be left to the CPU. Bring back the stack machine!

 

[Ncogneto]

That is not proof. Confusing it with proof is exactly the sort of fuzzy thinking that has so many people believing conspiracy theories, these days.


It's not a counter-argument, it's a statement of fact. And I didn't say you "can't prove", only that you haven't provided proof.

You are ascribing a motive. You need evidence that it was indeed their motive. You have not provided it.

I'm not going to continue debating this, because it's silly, off-topic, and amounts to nothing more than an irreconcilable difference of opinions. I have already stated my opinion and have nothing more to say.

It's called theory. Theory is not law. My theory provides us with the most logical explanation. Yours fails that test, and it fails incredibly.

Your argument that I cannot prove it is weak, and juvenile. I can't prove a black hole is not made of cotton candy either. I thought you were better than to end with fallacy, with an appeal to ignorance none the less.

In your scenario, Apple (a multi-billion dollar company) and a group of it's R&D team develops a product, wheels, and decide to sell them for $700 a set. They do this knowing at best they might hope to sell maybe 100 sets, and if things go really well, maybe 500 sets.

So Apple, (again, a multi-billion dollar company) stands to gain what exactly from this endeavor? A profit of maybe $200,000? hell, maybe $800,000? Hell, after the R&D, production costs, literature, etc etc, would they even make a profit at all?

Why would they even bother?

My theory provides a much more plausible explanation. They are called "Halo" products. Halo products exist not to make a profit on their own, but to add perceived value, buzz, and prestige down the manufacturers entire product stack. It's actually a pretty common practice.

Why do you think Intel is so desperately trying to hang on to their "fastest gaming CPU" crown?

And why is any of this relevant to the topic at hand?

Engineering vs Marketing. You need both.

 

[JayNor]

Looks like Intel may not have much for people to get excited about until 2022.

Intel announce successful power-on of 10nm petaflop Xe GPU.
Intel announced 2H2020 sampling of 10nm Sapphire Rapids server chips with PCIE5/CXL, DDR5, AVX512 bfloat16, AMX bfloat16, new Optane version support.

 

[JayNor]

Now TSMC are using EUV for 5nm.

but AMD is not using EUV yet. Why?

 

[JayNor]

I believe we have read rumours like Intel's 10nm is slower than their 14nm ( can't clock as high).

but that's also true for AMD... they haven't matched Intel's 14nm boost clocks with their TSM process.

Intel's 10n+ base clocking on Tiger Lake has improved, but benchmarks still don't show it matching Comet Lake boost clocks.

Looks like Intel will join the "more small cores" club next year with Gracemont, but Sapphire Rapids will be using bigger cores with the addition of AMX and AVX512 bfloat16.

 

[JayNor]

Listening to Intel 2Q Earnings Conference...
Intel is touting that they have the most technically advanced packaging technology... While their new 7nm process is technically screwed.
I could be wrong but that seems like wrong priorities </s>
Ridiculous!

Intel announced successful power-on of a petaflop Xe GPU, which stitches Xe chiplets and HBM. If AMD can't match it with TSM manufacturing, then AMD has a problem.

 

[MasterMadBones]

although the 3000-series also has the disadvantage that its L3 and memory controller are an earlier process node

The L3 cache is on 7nm as part of the CCXes. The disadvantage with Matisse is that DRAM is further away from the cores, which is why L3 is so large in the first place. Renoir's IPC should be similar as a result of reducing the cache size along with DRAM latency, but with the IMC on 7nm as well, there are indications that it is possible to get very high memory clocks with a 1:1:1 ratio.

Your argument that I cannot prove it is weak, and juvenile. I can't prove a black hole is not made of cotton candy either. I thought you were better than to end with fallacy, with an appeal to ignorance none the less.

I find it interesting how you proceed to make a slippery slope in the next two paragraphs.

The truth is that neither of you can prove your arguments, but both of you are trying to put the burden of proof on the other. The only thing I can say about this is that bit_user's argument seems like less of an accusation towards Apple.

I think it's perfectly reasonable for a company like Apple, which sells 'premium' products, to charge so much for "pro-level" accessory. It's a relatively low volume product, yes, but if there is demand for it, why not sell it? Why would they not have released the Mac Pro? People who need it, will buy it regardless of the price because that is how the professional market works. It's similar to how a graphing calculator costs as much as a budget phone while having far inferior hardware. There is money in people who need something from you.

 

[EricLane]

I just ordered an i7 10700k (ten minutes ago). With the bad Intel news lately, would anyone expect intel to lower prices in the near future and recommend I cancel the order and wait for a price drop? Or is that highly unlikely?

 

[MasterMadBones]

Intel announced successful power-on of a petaflop Xe GPU, which stitches Xe chiplets and HBM. If AMD can't match it with TSM manufacturing, then AMD has a problem.

Power-on testing is a relatively early stage of the validation process. We don't know anything about power consumption, yield, programmability or how those PFLOPS translate to real-world performance.

 

[MasterMadBones]

I just ordered an i7 10700k (ten minutes ago). With the bad Intel news lately, would anyone expect intel to lower prices in the near future and recommend I cancel the order and wait for a price drop? Or is that highly unlikely?

Intel never drops prices. They'd be more likely to launch a refresh. Regardless, I don't think either will happen because the current product stack is still looking competitive enough. They're also pretty much selling all the 14nm they can make right now, so a price drop will only reduce earnings.

 

[EricLane]

Intel never drops prices. They'd be more likely to launch a refresh. Regardless, I don't think either will happen because the current product stack is still looking competitive enough. They're also pretty much selling all the 14nm they can make right now, so a price drop will only reduce earnings.

I have bad luck with stuff happening like that, which is why I asked. Thanks for the quick reply and setting my concerns at ease.

 

[bit_user]

The voice of Itanium from beyond the grave! If we can't even rely on compilers to extract parallelism, what's the chance that they can properly manage CPU caches?

It's cute how you invoke Itanium to argue against something that sounds vaguely similar. Like, if somebody once tried something a little like what you're talking about, it's conclusive proof the idea can never possibly work.

Anyway, I hope you saw my link to Anandtech's coverage of the Elbrus processor. Perhaps we just need the Russians to show us how it's done. I should add that the comments are probably more informative than the article, itself.

 

[bit_user]

At the end of the day, only the CPU cores possess the information required to make optimal clock-by-clock decisions based on current machine state in an increasingly unpredictable environment.

Except we're not talking about "the end of the day". We're talking about "all day long", as in the program or the OS can continually monitor performance counters to see how often predicted branches were taken. When the program diverges from any of the optimized paths, it could trigger re-optimization. You can cache the code optimized for multiple different branching patterns and dynamically switch between them, as well. Given how much RAM browsers have grown to consume, I sometimes wonder if this isn't exactly what JIT Javascript compilers are doing.

The biggest problem with baking optimizations into the code or compiler is that the compiler/code cannot account for architectural changes that make formerly optimal code no longer optimal.

EPIC had a solution to this, which was still to rely on hardware-scheduling. They didn't take it nearly as far as they could've, as I don't think it ever did speculative execution or branch prediction, but there's nothing in the ISA that would've prevented doing so.

Letting the CPU make those calls gives a whole lot more design flexibility from code to silicon.

It also burns more power. So, when people decide they'd like to continue scaling datacenter capacity without boiling the oceans, we're going to have to unwind some of the fundamental decisions and assumptions underlying current CPU orthodoxy.

 

[bit_user]

Context switches would be impossibly expensive too, since we'd need to push/pop all cache levels.

I don't even know quite what you're talking about, at this point.

If you have some amount of on-chip scratch pad memory, it's probably not much and you would indeed have to spill at least some of it to RAM. Did you complain about context switching when you heard about AVX-512? I'm not necessarily talking about more than that amount of state, and it's state that currently exists in the cache hierarchy & RAM anyhow. So, the net effect is still less traffic through the cache hierarchy.

I think even register allocation could be left to the CPU.

I know people have experimented with memory-to-memory architectures, though I don't know if anyone ever did anything like dynamically substituting certain addresses with registers. I'm going to guess not, but who knows?

 

[Chung Leong]

Except we're not talking about "the end of the day". We're talking about "all day long", as in the program or the OS can continually monitor performance counters to see how often predicted branches were taken. When the program diverges from any of the optimized paths, it could trigger re-optimization.

That approach didn't get Transmeta very far...

 

[bit_user]

It's called theory. Theory is not law.

It's more appropriately termed a conjecture, as no proof is available to either confirm or refute it. In scientific terms, a theory is well-established by empirical evidence that would disprove the theory, were it not true. Very few ideas that people refer to as "theories" actually meet this standard, since it requires carefully-designed and controlled experiments, which are then reviewed and repeated by others.

Nothing you've presented as evidence or "proof" would even hold up in a court of law.

Apple (a multi-billion dollar company) and a group of it's R&D team develops a product, wheels, and decide to sell them for $700 a set. They do this knowing at best they might hope to sell maybe 100 sets, and if things go really well, maybe 500 sets.

If you believe those numbers and you think they didn't need to charge so much, then you don't seem to understand marginal costs.

Why do you think Intel is so desperately trying to hang on to their "fastest gaming CPU" crown?

A wheel kit and the designation of "fastest gaming CPU" are not comparable, in any way. People who buy a CPU for gaming are more likely to go with the brand having the designation of being the best for that purpose. They don't make decisions about whether to buy a Power Mac based on the price of its wheel kit.

The pricing and marketing of the machine, itself, is enough to establish it as a halo product. However, I don't think it much matters whether it's halo product. Indeed most people buying Power Macs likely have no other choice - they're either forced to use Mac OS apps, or simply refuse to use anything else, and need more horsepower than they can get from Apple's other products. It's a captive market.

I'll not dignify the rest of your post with a reply, as I find it highly inflammatory and I don't wish to escalate this further.

However, my primary reason for replying is to point out one observation that you can't disregard, if you're being at all honest with yourself. Linus had an incentive to put out that video, regardless of whether it's true or not. He needs to publish content to keep racking up views and subscribers, and there's no better way to do that than with a controversial claim that doesn't stretch credulity too much.

Well done, LTT. Bravo. We are indeed suckers.

 

[bit_user]

Intel announce successful power-on of 10nm petaflop Xe GPU.
Intel announced 2H2020 sampling of 10nm Sapphire Rapids server chips with PCIE5/CXL, DDR5, AVX512 bfloat16, AMX bfloat16, new Optane version support.

Promises, promises. Lately, their announcements haven't been worth the electrons used to transmit them.

They need to shut up and deliver.