News Intel at IEDM: Stacking Nanoribbon Transistors and Other Bleeding Edge Research

[Admin]

Intel has describes some of the work it has presented at the IEDM 2019 conference. The work includes innovation in packaging beyond its Foveros and Co-EMIB technologies and the stacking of germanium nanoribbons on top of FinFETs.

Intel at IEDM: Stacking Nanoribbon Transistors and Other Bleeding Edge Research : Read more

 

[InvalidError]

Making pmos on germanium and nmos on silicon then bonding two wafers to make one chip from otherwise incompatible materials. We're getting into real fancy territory there.

 

[digitalgriffin]

Making pmos on germanium and nmos on silicon then bonding two wafers to make one chip from otherwise incompatible materials. We're getting into real fancy territory there.

I was thinking the same. It will be interesting to see how it deals with {atomic} P state differences which often generate heat. Stacking chips in such a manner is already problematic with cooling. Adding in different materials with different electrical shell potentials, will make things "very interesting" heat wise.

 

[TJ Hooker]

It will be interesting to see how it deals with {atomic} P state differences which often generate heat. Stacking chips in such a manner is already problematic with cooling. Adding in different materials with different electrical shell potentials, will make things "very interesting" heat wise.

Can you elaborate on how a material with a different electron configuration would inherently generate heat, and how this would change by adding something like germanium? It would seem that "adding different materials with different electrical shell potentials" is something that is already done in conventional silicon CMOS, i.e. the dopants.

 

[digitalgriffin]

Can you elaborate on how a material with a different electron configuration would inherently generate heat, and how this would change by adding something like germanium? It would seem that "adding different materials with different electrical shell potentials" is something that is already done in conventional silicon CMOS, i.e. the dopants.

Sorry for the long delay. Christmas vacation and all.

Whenever you send electricity from one material to the next electrons bump around atoms. The amount of ionization energy varies from one metal to the next. For example silver takes less energy than copper and is therefore a better conductor.

When you combine two different metals like a peltier junction and pass a current through them an interesting effect happens. One side gets hot. The other cold.

This is also the reason intel swithed away from using copper wire interconnects to the package. Colbalt was closer to the native silicon in characteristics. Not only this but it reduced signal reflection due to micro differences in resistence.

That said doping of cmos transistors is a very effective way to create low power but slower circuits. Doing so over a long distance though creates the same issues. Because you are going from mat a to mat b to mat a, i would imagine the heating and cooling would cancel each other out. There are inefficiencies though and it generates heat. But i dont know the physics of why its more efficient for intel. Hence the mystery for me.

I always imagined a transistor like this...youre running along a road and you come up to a river. You cant cross that river till you have something to hop off of, like a floating raft in the middle. (Base) The bigger the float raft the more can go at once by bounce skipping off it. But if the river gets too wide (distance between collector and emmiter) you slow down and need more push (voltage). So while the raft allows you to cross the divide, it isn't as efficient as a solid road.

Im going to be honest and tell you this isnt my specialty. I do design some circuits but some basic sensors and data acquisition circuits.