goldstone77
Distinguished
Let me add some perspective to what too the last post I made. https://semiengineering.com/whats-after-finfets/
This shows at Intel's 7nm it will be at 37nm, which is below what IMEC has consider the tipping point for FinFet.
Here is another view of the different devices going smaller.
Looking at the chart below we can see the CPP at Intel's 7nm and other foundries 3nm.In theory, finFETs are expected to scale to 5nm as defined by Intel. (A fully-scaled 5nm process is roughly equivalent to 3nm from the foundries).
Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). ... TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch.
This shows at Intel's 7nm it will be at 37nm, which is below what IMEC has consider the tipping point for FinFet.
Here is another view of the different devices going smaller.