goldstone77
Distinguished
jimmysmitty :
I always thought the node name was based on the smallest possible part of the node and not just the gate length but I guess not.
I guess nm means nothing then and so long as Intel keeps density up they remain ahead of the game. They really need to get 10nm or 7nm out though. I am honestly surprised they have had this much trouble. They had 10nm ready years ago but I guess yields and leakage must be the biggest problems.
I guess nm means nothing then and so long as Intel keeps density up they remain ahead of the game. They really need to get 10nm or 7nm out though. I am honestly surprised they have had this much trouble. They had 10nm ready years ago but I guess yields and leakage must be the biggest problems.
According to Brian Krzanich, he claims that most of these problems are associated with multi-patterning and low yields.
We're slowing the ramp down as we go and fix these yields, and we're able to do that. A), we understand the yield issues. They're really tied to this being the last technology tied to not having EUV and the amount of multi-patterning and the effects of that on defects.
Read BK's statement in the spoilers from the earnings call, in the link below.So I'm just going to correct you. You said that supposedly we have the solutions. We do understand these, and so we do have confidence that we can go and work these issues, Stacy. Right now, like I said, we are shipping. We're going to start that ramp as soon as we think the yields are in line. So I said 2019. We didn't say first or second half, but we'll do it as quickly as we can based on the yield.
The last part of your question about whether will it be a 10 or 10-plus-plus or 10-plus I think was your question, the yield improvements that we're making are just that, more focused on yield. So think of them as improvements to the various edge stuff, the lithography stuff, thin cleans (33:54) and things like that in order to really drive the multi-patterning and, in some cases, multi-multi-patterning, where you have four, five, six layers of patterning to produce a feature. It's really about that. They aren't necessarily around performance.
http://www.tomshardware.com/forum/id-1581001/intel-future-chips-news-rumours-reviews/page-63.html#20920876
So, I think BK is saying that EUV might be able to fix some of the issues with yields, because of the multi-patterning. EUV is getting closer to being ready, but it's not ready yet. TSMC and Samsung are have been fairly transparent about how aggressive they are with using EUV. Intel has been less forth coming about the state of it's EUV program.