Intel's Future Chips: News, Rumours & Reviews

Page 132 - Seeking answers? Join the Tom's Hardware community: where nearly two million members share solutions and discuss the latest tech.
Status
Not open for further replies.


According to Brian Krzanich, he claims that most of these problems are associated with multi-patterning and low yields.
We're slowing the ramp down as we go and fix these yields, and we're able to do that. A), we understand the yield issues. They're really tied to this being the last technology tied to not having EUV and the amount of multi-patterning and the effects of that on defects.
So I'm just going to correct you. You said that supposedly we have the solutions. We do understand these, and so we do have confidence that we can go and work these issues, Stacy. Right now, like I said, we are shipping. We're going to start that ramp as soon as we think the yields are in line. So I said 2019. We didn't say first or second half, but we'll do it as quickly as we can based on the yield.

The last part of your question about whether will it be a 10 or 10-plus-plus or 10-plus I think was your question, the yield improvements that we're making are just that, more focused on yield. So think of them as improvements to the various edge stuff, the lithography stuff, thin cleans (33:54) and things like that in order to really drive the multi-patterning and, in some cases, multi-multi-patterning, where you have four, five, six layers of patterning to produce a feature. It's really about that. They aren't necessarily around performance.
Read BK's statement in the spoilers from the earnings call, in the link below.
http://www.tomshardware.com/forum/id-1581001/intel-future-chips-news-rumours-reviews/page-63.html#20920876

So, I think BK is saying that EUV might be able to fix some of the issues with yields, because of the multi-patterning. EUV is getting closer to being ready, but it's not ready yet. TSMC and Samsung are have been fairly transparent about how aggressive they are with using EUV. Intel has been less forth coming about the state of it's EUV program.
 
Samsung Electronics Co. is facing a hefty penalty for improper use of a FinFET technology patent. According to Bloomberg, a federal jury in Texas on Friday said that the South Korean electronics company infringed a US patent owned by the licensing arm of Korea Advanced Institute of Science and Technology (KAIST).

The jury told Samsung to hand over $400 million for damages, but the company could be facing three times that amount. Bloomberg reported that the jury found Samsung’s actions to be “willful,” which gives the judge the authority to raise the fine by as much as three times the jury’s figure.

Qualcomm and GlobalFoundries joined Samsung to defend the use of the FinFET technology. GlobalFoundries also manufactures chips with FinFET technology and Qualcomm is a customer of both companies. The jury found them both guilty. However, Qualcomm and GlobalFoundries were not ordered to pay any damages to KAIST.
https://www.tomshardware.com/news/samsung-400-million-finfet-lawsuit,37319.html
 
Intel's CEO is out.

Intel Corp. on Thursday said that CEO Brian Krzanich has resigned, and the board has named CFO Robert Swan as interim CEO.

The resignation comes after Krzanich disclosed a past consensual relationship with an Intel employee, and an investigation confirmed that it violated Intel's non-fraternization policy.

The board has begun a search for a permanent CEO.

https://www.cnet.com/news/intel-ceo-resigns-cfo-will-serve-as-interim-chief/
 


Seems like nowadays is better to be a horny CEO rather than an incompetent one?

Cheers! 😛
 


Those policies always strike me as weird. If it is a consensual relationship then who cares? The only issue are the ones with coercing in them or abuse of power.
 


The danger is always that a manager will either take advantage of or give additional benefit (promotions and whatnot) to employees who work under them. Generally, companies are OK as long as it's cross department, but enough have been burned in the past where some outright outlaw it.
 
Brian Krzanich out as CEO of Intel
Bob Swan is in the new hot seat
Jun 21, 2018 by Charlie Demerjian

It looks like Intel’s CEO Brian Krzanich is out, replaced by Bob Swan. SemiAccurate thinks there is a lot more to this story than a past consensual relationship though.

In a terse release today, Intel said exactly what SemiAccurate just said, just in a lot longer form. Officially BK violated Intel’s non-fraternization policy, something which SemiAccurate strongly doubts lead to this ousting but it sure makes a good cover story. That said, technically it is a firing offense, but given the conduct of past people in the same seat and the consensual nature claimed, it should have revived a low end of the scale punishment.

Why do we claim this is a cover? Intel’s 10nm process flat out doesn’t work. The company is about to lose huge chunks of their core server market to AMD and has no way out. Their current efforts to hold the line and prop up margins have seriously alienated customers and there is no end in sight for the slide. To make matters worse, their roadmaps are a complete mess and change faster than the ink can dry. Some have even suggested that Mr Krzanich knew the train was about to run off the rails, we sure did.

When times are tough and faith is about the only thing holding your stock at it’s current highs, the last thing you want to do is fire your CEO for cause. Intel has some very smart people on their board and in upper management, they know this. That said they needed to do something and, well, a slap on the wrist offense becomes an interim CEO. There is much more to this than a simple consensual affair, when the depths of Intel’s woes become clear, so will the reasons behind this transition.S|A
https://www.semiaccurate.com/2018/06/21/brian-krzanich-out-as-ceo-of-intel/

Intel CEO Brian Krzanich Resigns; Board Appoints Bob Swan as Interim CEO
Second Quarter Revenue and Non-GAAP EPS to Exceed Prior Guidance; 2018 to be Another Record Year
SANTA CLARA, Calif. – June 21, 2018

https://newsroom.intel.com/news-releases/intel-ceo-brian-krzanich-resigns-board-appoints-bob-swan-interim-ceo/
 
That is something I don't think, at this point, anyone can really do...

I mean, Intel is already screwed with 10nm and I don't think the board is willing to give the shekels to help the situation. Hell, I don't even think funneling money to the Fab problem will help. They've known about the problems since long ago, but haven't found solutions yet, so sounds like it's not a "throw money at it" type of thing.

Also, they've been at the very top for far too long. Monopoly top even. With *zero* interference. AMD just did not push them for 5 whole years. FIVE YEARS. They took everything from AMD in terms of server market share and, to a degree, consumer. Intel has no other way but to go down from there if AMD (or any other) starts doing the right things.

The problem with Intel right now is how the board is taking the bad news and, for me at least, is clear that BK did not deliver a message they liked.

Cheers!
 
We know 10nm has issues. We have no idea knowing if they have a solution or not or if they plan to push past it. I mean FAB 42 is 7nm now. Plus Intel does have a 10nm part in the wild in China, of all places.

That said it would take time but there is a possibility for a better CEO to help steer the ship to a much better direction.
 
Great leadership is absolutely needs to right the ship, history if filled with powerful transformative leaders. The problems lies with TMG's management failing to deliver on 10nm, and/or lack of keeping the CEO in the loop. It's the CEO's fault for not fixing the problems, and/or not making the right decisions. If they can't fix 10nm I doubt they will be able to fix 7nm. They had to pull 10nm people in to fix 14nm. If the problems surrounds not having the capability of using EUV like BK suggests, than it will take EUV to fix the problem. And that is still a few years away from maturation for volume production. The very small release of 10nm dual cores performed worst than 14++ with the same power draw while lacking a functional iGPU. I think the BOD pushed BK out, because they could no longer hide his incompetence. At this point, TMG become an ever growing liability for core business, and it's possible Intel might have to start outsourcing production of it's processors to another foundry. This hinges on what BK said about the readiness of EUV being able to save these 10 processes, or at least save 7nm in the future.
 
I can't find a way to word this better, so here it is: the CEO cannot save the Company if one of the core areas/departments/teams can't pull their own weight and can't be helped from the outside.

I really don't think Intel needs a change of direction, they just needed fresh ideas in what they're already good at: fab+design. Gamerk has a good point here: maybe leaving Core to live this long was detrimental to all the problems that exploded at once. The Fab problems, I think are a problem of not telling the upper chain of command they were clueless (they weren't, I'm sure, but...) about how to face the problems they had. I've read a lot about how Intel's culture did not let them seek "help" from the outside (I doubt this TBH) and tried to solve it in-house at all costs. Plus all the other things that might go on at such a huge mammoth of a Company.

Analyzing the little pieces allows you to put them together better: BK just had no idea what to do and could not capitalize on any of Intel's strengths to implement quick change where needed (not a change of direction, I insist). It could have been he had the ideas, but the teams could not pull ahead, or that he did not have the ideas nor the team had them and they were just banging their heads against the wall.

If there's to be a new CEO, Intel won't be able to really do anything until the end of 2019. As a "new direction" type of thing. Which I don't really think is necessary TBH.

EDIT: TSMC is saying they're ramping up already!
https://techreport.com/news/33843/report-tsmc-ceo-says-7-nm-production-is-ramping-up

Cheers!
 
I have no idea whats going on behind scenes. We don't know what they might have planned.

I am till curious if they were having these problems why they invested so much time and money to convert FAB 42. There has to be a reason behind it.
 
rPXufGu.png

https://twitter.com/witeken/status/1010282236229357568
 


I can take some guesses.

We've been seeing Intel start to fall behind in it's fab tech for a while now, starting when it's tick/tock got extended to 18 months. The fact things have gotten this bad with 10nm shouldn't be surprising in hindsight; Intel is one of those companies that tries to keep things "in house", which is good when you are technically superior, but not so good once you start to fall behind. Intel's now at the point where they are technically behind most of the other fabs, so they either need to bring in people who know how to fix things, or start outsourcing production. And from a company culture perspective, both are hard sells at Intel. We'll know how the board feels when they elect a permanent CEO, specifically, look to see if they get an outsider or not.

As for Fab 42, I think Intel may be preparing to skip 10nm and try to jump directly to 7nm. If their 10nm yields are that bad, even an immature 7nm process might be a better bet then trying to fix 10nm.

As I've noted: die shrinks are getting ridiculously expensive to pull off; it's very interesting we're almost at 7nm yet we've heard nothing about 4nm. (Hell, has anyone confirmed we can even DO 4nm with existing technology yet? Last I heard, the consensus was "maybe".)

And one final point: Intel recently showed up a full wafer of Quantum CPUs built using existing technology on the 300nm node. There's the outside possibility that Intel could just forgo die shrinks going forward, and move exclusively into Quantum chips built using silicon on existing processes. As of today, AMD (and pretty much everyone else) wouldn't be able to compete if Intel pulled that off.
 
^Thats some interesting info.

If Intel does just jump right to 7nm they will still be ahead even if the naming isn't as they will be near 2x as dense.

Guess we shall see in the near future. I am sure they are planning something. Our company did provide some materials for some of the new work at FAB 42 so who knows. Maybe we will get a new Core 2 like launch which might push AMD again. Hopefully. Or not. Who knows.
 


Other foundries have will be on 3nm probably before Intel will have 7nm, and some are suggesting they will skip 10nm all together to get 7nm out ~2021-22. It's hard to guess, because we don't know what Intel is going to do yet. Other thoughts seem to be that Intel would be better off outsourcing their core business to foundries like TSMC, so they can stay competitive. They wouldn't give up the foundries completely, but they would continue to make what they can. Let's see who they pickup as their new CEO. Some speculation seems to be on Navin Shenoy.
Navin Shenoy
https://newsroom.intel.com/biography/navin-shenoy/
 
I will stand by my comment that Intel has no other way but to go down, but on the bright side (for them) they have plenty of options (and cash!) to actually steer the boat wherever the hell they want to.

Gamerk raised a couple interesting points around Quantum Computing and the huge opportunity they could get from it. They also have the 10nm skip and get in talks for licensing to get the 7nm node running sooner with their current targets (might be cheaper in the mid-term). And even, like I jokingly said before, just go back to solder and just clock the CPUs higher until they get their house ordered. I would not put it past they have the next uArch almost ready to go (as in, fab it soon), but the 10nm problem has put breaks around it.

Cheers!
 


I don't think Intel has a replacement uarch ready to go, based on their past roadmaps that had Core existing for a while yet. I'm sure they are currently working on one, but I'd be shocked to see something "new" within the next 5 years.
 


Ice Lake is not backward portable. This shows you how much Intel uArch design's are dependent on process improvements! BK pinned most of the problems on multi-pattern, and not have EUV. I would keep a close eye on EUV readiness. Also, Intel hired Raja/Keller for a reason, expect something spectacular to come out of that ~3-4 years, but this also hinges on if Intel will have access to a competitive process to build on.
 


So long as other foundries don't run into similar issues with their processes at "3nm" it is possible they will have it first. But again there have been times where Intel is pretty quiet and something random comes out.

I like the current state but hope Intel doesn't fall behind. They have the resources and experience to push faster than most do.



I am sure they have multiple projects they are working on. One issue with having a completely new uArch, as seen with Itanium, Netburst and Bulldozer, is that there is a lot of risk that it wont perform. SO I am sure they would be much more cautious so as to not shoot themselves in the foot again.

Granted Itanium would have been good if it didn't have the x86 performance drop but that was the only way to do a pure 64bit uArch.
 


That is a good point to make, since it will require new device technology. The timelines are a little outdated, but ASML shows some of the leading ideas for devices while the process shrinks. We would assume Intel will also face these same challenges. Note that TSMC and Samsung have already produced 10nm, which is more dense than Intel's 14nm. And TSMC is producing 7nm in volume now, with it's first products to come to market 2H2018. This is fairly nice lead on everyone else in the industry.
Db5zAjMXkAc6a9o.jpg

It appears that foundries, other than Intel, are leaning towards nanosheets. As of now it appears Intel is still trying to use FinFet.
MjkwODYxNA.jpeg


What’s After FinFETs?
Chipmakers exploring nanosheet, nanoslab, nano-ring and hexagonal FETs.
JULY 24TH, 2017 - BY: MARK LAPEDUS

"The big decision comes when the gate-pitch approaches 40nm. Based on simulations from Imec, the finFET begins to teeter at a 42nm gate-pitch"
https://semiengineering.com/whats-after-finfets/
 
Status
Not open for further replies.