Intel's Future Chips: News, Rumours & Reviews

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aldaia

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Intel puts out another 14nm 2020 server platform
https://semiaccurate.com/2018/09/11/intel-puts-out-another-14nm-2020-server-platform/

I guess that means that after cascade lake (late 2018) and cooper lake (2019 probably Q4), there is yet another 14nm server product in 2020 before we see 10 nm ice lake ... which has chances to be delayed well into 2021
If this is the case AMD will have a great time in the server space.
 


You are forgetting that there is a lot more than just putting a new server in. There is a whole host of tools that work in very specific ways. For example VMWare, which most companies use, cannot mix and match brands. No major company is going to swap out every server at once. Maybe location by location but it would be more costly to deploy a new server and reprogram everything to work with AMDs system than to just implemnt a new Intel server.

Now over time if they remain competitive and don't fall behind like they did with Bulldozer/Piledriver, they could take some market share but they will not go from 1% to 50% in a year. There is just so much more to it than that.
 
That sounds more like a confirmation on what Charlie from SA mentioned a while ago, doesn't it?

I'd like to know more about Intel moving EUV forward and try to make a less restricted/perfect "7nm" node.

Cheers!
 


I am never a fan of "anonymous" sources. They could be the janitor for all we know and he is just going based on low level talk.

I understand they want to protect their job but why even put this out at all? If you work for a company unless you are exposing a crime just let it come out naturally.
 


The named sources thing is not a bad idea to follow, but it's better the cross-reference idea for these sort of things. Plus, as long as it is presented as single-source rumor it's fine. Like you're doing now, you can just discard it as noise.

As I said above, it matches what Charlie said more than create a "new" rumor.

Cheers!
 

aldaia

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Acording to adoredTV EPYC 2 Rome will be 9 dies. 8 tiny core dies (with 8 cores each) + 1 uncore die
If that is true, expect one of those tiny dies to be the basis of ryzen 3 series processors.

Annother interesting rumor is that Zen2 core is not an evolution of Zen core, but a total new design from the ground up.

https://www.youtube.com/watch?v=KVXDOWy4vTU

Also Cooper lake is assumed to be two dies "glued together" .
 
Uhm... 8 dies + 1 un-core die... Seeing how much power the mesh in Milan uses, then to push all those interconnections, it won't be a "low" power CPU by any means. Now, to reach that many cores I would imagine there's little alternatives left other than that, except 4+1 with 16c per "core" die.

From 14nm to 7nm, given how GloFo was using Samsung's process and TSMC offers really good measurements for their 7nm, I think it's not that un-thinkable AMD was able to pack 8-12 cores per die now. I'd even say 16c per die is not that really off imagination if they really made the un-core separate. Depending on how you design the topology, you can really squeeze the space between the cores I'd say.

Also, I don't think AMD made Zen2 from the ground up. That's un-thinkable. I do believe they just grabbed the "core" design and re-did all the interconnects with IF and moved everything they could out of it.

Thinking about Server loads as well, they better feed those cores with dedicated memory channels, otherwise they'll fall short on a lot of important metrics. Leaving the IMC centralized and adding more logic there is fine and all, but latency sensitive loads will complain.

There's a lot to analyze from the video and rumors on Rome, but I personally don't think they'll make too many chiplets this time.

Cheers!
 

aldaia

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Intel is Serving Major Xeon Discounts to Combat AMD EPYC
https://www.servethehome.com/intel-is-serving-major-xeon-discounts-to-combat-amd-epyc/
 

aldaia

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Intel / Micron have yield issues with QLC 3D nand flash. Commercial availability of 96 layer NAND may be pushed to next year.

A source close to the situation stated the current yield for 64-layer QLC is hovering right around 48%. Less than half of the die manufactured are reliable enough to use in an SSD. In contrast, current 64-layer TLC from IMFT has a yield right around 90% as of today.
Read more: https://www.tweaktown.com/news/62984/intel-micron-qlc-flash-yields-less-50/index.html

Note: I think they mean 96-layer QLC and not 64
 
Uhm... What are the next major technological symposiums coming? CES? Something before XMas? xD

Maybe by then we'll have more information on how screwed 10nm is for Intel and what they're really planning after actually eating it up and acknowledging it was a mess.

Cheers!
 

aldaia

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12 years after Intel said no to the iPhone you can buy an x86 iPhone. Lol
Yes you read well, all newest iPhones have an x86 inside, ....... to control the XMM 7560 modem :ouch:
https://lcq2.github.io/x86_iphone/
 
It could be VIA providing a micro-controller there for the modem. That ASM doesn't have anything from the new X86/64 uArchs really, so it could be a really stripped down (read: basic) X86 CPU. Or even just a RISC based CPU that just uses the X86 ISA.

Cheers!
 

aldaia

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Nope, not VIA.
The processor is integrated into the modem. The XMM 7560 used in the newest iPhones is fabbed by Intel.
https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xmm-7560-brief.pdf

Previous Intel LTE modems had ARM based controllers. It just seems they replaced ARM by x86 to save on licensing fees. Notice that x86 is mentioned nowhere in the XMM 7560 documentation since nobody cares what processor controls the modem.

The Irony here is that:
In PCs the main CPU is a beefy x86, while there are plenty of tiny ARMs everywhere (fon instance in the SSD and/or HD controllers)
In the upcoming iPhones the main CPU is a beefy ARM while there is a tiny x86 controlling the modem.
 


I wonder what the performance metrics are. I know that in terms of NICs you are best off with an Intel NIC for the best possible performance and their wireless also tends to be pretty top of the line.
 
There's also a question around power usage.

That would be a more interesting take on this: Intel is saving money, but at who's expense? Is the solution better for using X86 or worse? Same?

I still think Intel can be using a reduced X86 set and made a special RISC-based (read: fixed length decoder) for it instead of the usual CISC uArch we'd immediately think about.

Cheers!
 


That doesn't look like a normal Intel slide so I would be very suspicious of it.
 


Given the fact we're basically at the end of die-shrinks, meaning that die space is going to become VERY precious, I wouldn't be terribly shocked to see a major move toward RISC designs. The days where you can just stuff more transistors on-die to get performance is coming to an end.
 


We are at the end, and have known for a while, of Silicon die shrinks. There are other materials that could go beyond silicon but if they are usable is where we stand.

Then there is the possibility of stacking transistors which we have seen, HBM for example, but then comes the power and heat issues that arise from that.
 

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