Archived from groups: comp.arch,comp.sys.ibm.pc.hardware.chips,comp.sys.intel (
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Bill Todd wrote:
> In 'Beyond Superdome", he first waxes poetic about current Superdome
> capabilities, such as their internal interconnect fabric. Let's see: this
> is the server architecture (at least somewhat reminiscent of the old and
> rather mediocre GS320 server architecture) that using 64 top-of-the-line
> Itanics barely manages to stay ahead of the new POWER5 box that requires
> only 16 processors (on a grand total of 8 chips, since they're dual-core) in
> TPC-C, right?
I believe you have misinterpretted the "16 processor" POWER5. IBM
actually refers to chips. "16 processor" as reported is 16 POWER5
chips, comprised of 32 cores, allowing 64 threads of execution. So the
64-thread Madison vs the 64-thread POWER5 having similar performance is
just a sign that things are about equal. I'm stunned by how good POWER5
is. But I know that next year Montecito will go from 1 thread per
package to 4 threads per package. Itanium will be down to a 16P system
to compete with IBM's 16P system.
> Then he crows, "HP delivers dual core before Intel" as some kind of
> significant achievement. Well, maybe. Of course, Sun is delivering
> dual-core SPARC processors today, and IBM started delivering dual-core
> POWER4s nearly three years ago. So what beating Intel to the punch mostly
> proves is just how far behind the curve Itanic really is, I'd suggest.
And Itanium being behind the curve is a joint decision between intel and
HP, pushed by HP. If not for staffing levels on Itanium a few years
back and HP pushing to be the first to do the interesting dual-core
project, there would have been a dual-core Itanium 2 on the market last
year.
> Doubling
> current system performance by about a year from now actually sounds pretty
> impressive, until you recognize that Superdome's TPC-C performance today
> with 64 processors falls slightly behind today's previous-design-generation
> POWER4+ systems that use only half that number of processors and only
> slightly manages to beat today's POWER5 boxes that use only 1/4th as many
> processors.
As explained above, if you compare per thread, these machines are
equivalent in size (64P Madison, 32P * 2 cores POWER4+, 16P * 2 cores *
2 threads POWER5).
> When Montecito comes along late next year
> it will indeed close much of this gap with POWER5 (Terry's second
> TPC-C-specific performance graph suggests it should slightly exceed 2
> million tpmC), but POWER5 (a full process generation behind Montecito but
> still heading for about 3 million tpmC late *this* year) will no longer be
> IBM's top-of-the-line product by then, since POWER5+ (in the same process
> generation as Montecito) should then be shipping and upping the ante
> significantly.
I have not seen these graphs. Could you tell me what configuration
those X million tpmC results are for? 4P, 16P, 64P, 64 *thread*. How
are the estimates being made. I don't have a lot of TPC numbers, but I
know a 4-socket Madison today is 121K and a 4-socket POWER5 (yes, that's
16 threads) is 371K and Montecito is supposed to also be around 370K in
4-socket. It will be a tight race. If you could explain the
configurations, that would help me. If you could quote published
4-socket numbers for POWER4 and POWER4+, that would help me (I'm trying
to make a table).
> And Fujitsu has regular enhancements to SPARC64
> coming along to keep pace with Itanic (though not POWER), regardless of what
> one may think of Sun's future efforts for that architecture.
> SPARC is dead, eh? Or 'no longer relevant', as a later slide says.
> Someone better tell Fujitsu so it will stop stomping all over the
> latest Itanics in commercial benchmarks like jbb2000: that's really
> not suitable behavior for a 'dead' processor. And by all means make
> sure those HP customers who are defecting to Sun know this: what on
> earth do you suppose they're thinking?!
Fujitsu is far ahead of Sun in performance, but they are far behind even
the laggard (intel) when it comes to features. They say dual-core at
end of '05, dual-core with 2 threads each sometime in '07. Compare that
to Montecito which is mid-'05 with dual-core and 2 threads per core.
Two years ahead. What Fujitsu *does* have that keeps pace, or even
stays ahead, is RAS. I don't have much hope for the SPARC family going
ahead. Niagra and Rock could either be a revolution or a flop, but I
think that if Sun sticks with SPARC-64, it will drag them to the bottom
of the ocean.
Itanium is a lousy performer in Java. That is because Java employs
self-modifying code and the Itanium spec explicitly states you can't do
that. It was shortsighted to put that in, but they hoped to escape the
IA32 complexities self-modifying code added to the design. It cost them
vast amounts of performance. It was analyzed and Montecito should have
much better jbb results as they've added new instructions and features
to directly speed up SMC. After all, intel targetted Sun when they
marketted Itanium. To leave Java performance in the shitter would be
marketting suicide.
> Well, given that 'about now' is upon us and I don't see any "Alpha/IA64
> hybrids" being benchmarked, 2007 seems at least a lot more credible. I
> guess my prediction of 2006 three years ago was slightly optimistic, but for
> a 5-year-out guesstimate I don't feel *that* ashamed of it.
Yeah, having "hybrid" designs now was always BS. It was from an
external guess with no information. Assuming the Alpha folks were
divided up and sent to each project being worked on in 2001, there might
be Alpha concepts coming out now, but intel kept the Alphans together
and gave them a new project of their own that wasn't on any roadmaps in
2001. Shannon just couldn't have known that and spread his rosie ideal
picture of the future. It was unprofessional to report on what he'd
like to see rather than what he knows, but it's common practice.
Alex
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