"3D DRAM" refers to DRAM being manufactured with a "3D" process. The goal of 3D manufacturing processes is to make better use of physical hardware restraints by "stacking" dies, memory modules, etc on top of each other. Over in the world of CPUs, for example, we have something called "3D Cache", which refers to regular CPU L3 cache that's "stacked" in manufacturing to improve onboard memory capacity. And of course, Samsung pioneered 3D stacked NAND (Samsing calls it V-NAND) for SSD storage more than a decade ago.
First, V-NAND isn't merely die-stacking. This article from 2017 explains how Samsung fit 512 GB into a package by stacking 8x 64-layer V-NAND dies.
Second, die-stacked DRAM isn't new. Server DIMMs had it, going back at least as far as DDR4. HBM uses die-stacked DRAM, and that's been around for about a decade. Most recently, I believe Apple has been using die-stacked memory, in its M-series SoCs. So, let's assume they're not talking about "simple" die-stacking, here.
Probably the most plausible explanation is here:
It was in 2021 that Korean semiconductor makers officially started to talk about 3D DRAM development. It coincided with the time when Samsung Electronics started research by establishing a next-generation process development team within its DS Division in 2021.
3D DRAM is a memory chip with a new structure that breaks the current aged paradigm. Existing DRAM product development focuses on increasing integration by reducing circuit line widths, but as line widths entered the 10 nm range, physical limitations such as capacitor current leaks and interference increased significantly. In order to prevent this, new materials and equipment such as high dielectric constant (high K) deposition materials and extreme ultraviolet (EUV) equipment were introduced. But the semiconductor industry believes that miniaturization to make 10 nm or more advanced chips will cause great challenges for chipmakers.
The line width of cutting-edge DRAM that Samsung Electronics and SK Hynix will mass-produce this year is 12 nanometers. Considering the current situation where the line width of DRAM miniaturization is being reduced by one nanometer, commercialization of DRAM with a new structure will become a necessity, not an option, three to four years from now.
Source: https://www.businesskorea.co.kr/news/articleView.html?idxno=110830
So, I think they're pretty clearly talking about building multiple layers of DRAM cells
within a die. Either that, or at least changing the shape of the cells to be more vertically-structured, in order to increase the areal density of a single layer.
A related-sounding (but probably different) effort I recall reading was about Samsung (I think) partnering with Nvidia, to build processing dies that sit at the base of HBM-like DRAM stacks. I'm pretty sure I saw an article about it on here, but I'm unable to find it right now.
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