Semiconductor Production 101

[dasickninja]

Since the article links to the tread, why lock it to the top page?

 

[Sublimate]

GaAs? Not everything is on Silicon ya know...

 

[dasickninja]

Maybe not for this thread per say, but possibly have Jack and others (like Joset, wherever he maybe, Pippero and cxl) work on combining their knowledge of process technology and such and posting it, then if the mods approve, having it stickied.

Just my way of doing things.

 

[dasickninja]

Before we get back to discussing the topic at hand, (well, actually it would be you guys discussing this and me just watching and learning) note that seeing as this is a "official TG thread", most likely the mods would have prestickied the thread.

This is the end of me fouling the thread.

 

[anticupidon]

thanks for a very interresting and very neat article
well seems that the old saying back to the roots....gives again good results.
keep it up that way
MAKE IT A STICKY ! :trophy:

 

[CousinVinnie]

To Lbax

I understand steppings to be revisions of the dies. I have been of the impression that there are different magnitudes of steppings (i.e. A2 > A3 vs. A3 > B1).
What is subject to change in a minor step? (Process Tweaks - ie doping specs?)
What is subject to change in a major step? (Masks?)

Ax --> Ay transitions are called revisions and usually are related to minor bug fixes (device level), enabling/disabling of device features. They are not related to the die/field size change of the silicon device. Usually A0 are rerely making it to the customer as these are pilot vehicles.

Ax --> B0 is called stepping change and usually invoolve Si-related bug fixes (new transistors added/removed etc.) as well as signal routing changes. These may involve die size change.

Revision/Stepping change doesn't necessarily means that manufacturing process has been changed.

During revisions only a subset of lithographic masks is being modified, whyle stepping usually include full layer rehash.

Enjoy,

CousinVinnie

 

[Sublimate]

yay a technical article, i like these and also the ones where you visit places and we get a peak inside. perhaps a peak inside an actual FAB could be arranged.

if i was being picky i would have also like a flow chart of the processes involved as maybe it is just me but a diagram is always easier than words for showing the big picture.

All the fabs I have been in keep layouts and flows strictly confidential. Every fab has a NDA of some sort. A lot of processes are patented by the manufacture. When I am at a customer I can not tell them how someone else does things.

Processes are divided from Front end of the line to back end of the line . FEOL is anything before the first metal layer, after that is is considered BEOL. Lithography is obviously not confounded to these guide lines. Most tool sets are split to avoid cross contamination of metal.

The generic processing of wafers is no secret, you could probably easily dig one up by using google.

Sub

 

[enewmen]

It takes over 300 individual production steps to make a microprocessor out of sand. We look at the fundamentals of what is involved.

Very appropriate article for Toms HARDWARE guide.
Helped explain some mysteries also..

 

[gm0n3y]

I actually liked this article so much that I got the author this:

EDIT: All this talk of cookies and wafers is getting me hungry.

 

[CousinVinnie]

yay a technical article, i like these and also the ones where you visit places and we get a peak inside. perhaps a peak inside an actual FAB could be arranged.

if i was being picky i would have also like a flow chart of the processes involved as maybe it is just me but a diagram is always easier than words for showing the big picture.

All the fabs I have been in keep layouts and flows strictly confidential. Every fab has a NDA of some sort. A lot of processes are patented by the manufacture. When I am at a customer I can not tell them how someone else does things.

Processes are divided from Front end of the line to back end of the line . FEOL is anything before the first metal layer, after that is is considered BEOL. Lithography is obviously not confounded to these guide lines. Most tool sets are split to avoid cross contamination of metal.

The generic processing of wafers is no secret, you could probably easily dig one up by using google.

Sub

In addition, there are different types of devices (for example CPU's vs. Flash) and process requirements are way different for them. There are also different types of starting materials (epi Si vs. Si on isolator SOI wafers) and different types of transistors, which require absolutely different processing steps. The best way will definitely be some literature or even Wikipedia

CousinVinnie

 

[dietzjack]

Sometimes in news stories you will see that a processor has been "Taped out." Apparently this is one of the steps on the Concept->Release to market continuum. What exactly is meant by the term?

 

[gm0n3y]

I think that has to do with creating the mask, I'm not certain though, and I'm not sure where the term comes from.

 

[CousinVinnie]

Sometimes in news stories you will see that a processor has been "Taped out." Apparently this is one of the steps on the Concept->Release to market continuum. What exactly is meant by the term?

The termin "tape out" is coming from the days when storage media was magnetic tape. At the end of device development the product design engineers were transfering data from design center to mask shop by physically taking the tapes with the mask writing information to the mask shop.

Now all the data is transferred electrinically and termin "tape out" is used to mark the data release from design to the mask shop.

CousinVinnie

 

[AgnostiC]

I have been kind of in the shadows here at Tom's.Just reading in the forums.As you can see this by this being my first post,but I'll have to say I found the article to be pretty informative,could of went into some of the techniques a little deeper.But as Ninja said its about time they drop a good article on us.

 

[Shadow703793]

This is all good. But what we really need are the details at the ATI/AMD event 😀

 

[AgnostiC]

Wow that is weird,unless I have a ghost I could of swore that was my first post,but post count says 9.Anyways.

 

[testbenchdude]

Intel Fab22 (AZ) bay 217, Fron-end of the process. 200mm wafers, 130nm process. Made P4, Itanium, Chipsets. Processing tools shown: Right: TEL Dry Etcher-spacer, contacts, poly hard mask, End: SCP Global Wet Etcher-nitride clean, poly clean, Left: Novellus -resist Asher. There is also a Hitachi-Poly Etcher on the right front, not shown, and Left front is a surfscan machine.

Alas.. No Lam Research tools... YET...

😉

Actually, this was a pretty good article. I happen to work in the dry etch process and I gotta say that it's neat to actually see the plasma working on the wafers in the chamber. Yes that's right; there are view ports on most chambers that are UV and EMF shielded that allow you to see what's going on in there. It's like being able to see inside a fluorescent light bulb, and depending on what gases are being introduced, the plasma glows with different colors.

Also, turbo molecular pumps are fun (and scary) to work with. Just once I want to put a marshmallow in a chamber and see what zero atmosphere does to it...

 

[Sublimate]

Intel Fab22 (AZ) bay 217, Fron-end of the process. 200mm wafers, 130nm process. Made P4, Itanium, Chipsets. Processing tools shown: Right: TEL Dry Etcher-spacer, contacts, poly hard mask, End: SCP Global Wet Etcher-nitride clean, poly clean, Left: Novellus -resist Asher. There is also a Hitachi-Poly Etcher on the right front, not shown, and Left front is a surfscan machine.

Personally I could never tell if i was in Oregon or Rio rancho with the copy exact philosophy. I believe Chandler is 300mm now. Its been years since I have been in a Intel Fab.

neat to actually see the plasma working on the wafers in the chamber

LOL... look at the pretty lights burn your retinas out. Actually the quartz blocks 99% of harmful UV. You can tell gas in the chamber by the color of the plasma too.

Also, turbo molecular pumps are fun (and scary) to work with. Just once I want to put a marshmallow in a chamber and see what zero atmosphere does to it...

Not scary, just don't open to atmosphere and turn it into a canister of BBs.

its sub atmospheric mostly measured in Torr or mmHg. Atmosphere = 760 Torr. You could do a simple experiment at home with a soda bottle and a small pump.

Sub

 

[mordenkhai]

Fantastic article. Enough info for us newbies to feel like we learned something but not so much that I got confused.

I still cant fathom how people developed these concepts and processes from nothing.

 

[Dahak]

Good info for someone trying to decide if they want to go into the semiconduction business.Or for someone just lloking to enhance their knowledge a bit.

Dahak

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[CousinVinnie]

to JumingJack

In your point above, I have read about spin on glasses, and solgel chemistries that can do SiO2.... but I have not read any information on who does what technique, by far the most common oxides are CVD, some with TEOS, and thermally grown in furnances....

Spin on Glass (SOG), which is basically SiO2 in the liquid like state is used usually for back end process of lithography - dual damascene types of processes. You can find some info about it here:

http://jjap.ipap.jp/link?JJAP/40/7077/

CousinVinnie

 

[Paul_gren]

Nice article... It could have been a little more detailed but i still enjoyed reading it.

How about an article about case study (let's say Core 2 Duo) with more details and costs/step involved?

in that way we could make ourselves an idea of the investment made by AMD & Intel into manufacturing...

Paul

 

[BT]

Intel Fab22 (AZ) bay 217, Fron-end of the process. 200mm wafers, 130nm process. Made P4, Itanium, Chipsets. Processing tools shown: Right: TEL Dry Etcher-spacer, contacts, poly hard mask, End: SCP Global Wet Etcher-nitride clean, poly clean, Left: Novellus -resist Asher. There is also a Hitachi-Poly Etcher on the right front, not shown, and Left front is a surfscan machine.

Alas.. No Lam Research tools... YET...

😉

Actually, this was a pretty good article. I happen to work in the dry etch process and I gotta say that it's neat to actually see the plasma working on the wafers in the chamber. Yes that's right; there are view ports on most chambers that are UV and EMF shielded that allow you to see what's going on in there. It's like being able to see inside a fluorescent light bulb, and depending on what gases are being introduced, the plasma glows with different colors.

Also, turbo molecular pumps are fun (and scary) to work with. Just once I want to put a marshmallow in a chamber and see what zero atmosphere does to it...

If I am correct with the FAB, Fab 22 only has 4 LRC etchers for PAD Etch. The very end of the process. I hate those damned tools. TEL and Hitachi do all those dry etching for the front and back end. STI, Poly, HM, Spacer, Contact, Via, Trench, Nitride. That is for 130nm, 65 and 45nm are Top Secret, and radically different.

 

[BT]

Personally I could never tell if i was in Oregon or Rio rancho with the copy exact philosophy. I believe Chandler is 300mm now. Its been years since I have been in a Intel Fab.


I see too many small details that match what is in Fab22. I am pretty sure of it. Fab12 is 300mm 65nm, Fab22 is 200mm 130nm, Fab32 is 300mm 45nm.

 

[immagikman]

Nice article which would have been a better read if someone had proof read and edited the copy 🙁


Where is the quality?

You know two things I would like to have, just because I'm a geek, is a polished 200mm or 300mm wafer and a whole mono-crystal