News TSMC's wafer pricing now $18,000 for a 3nm wafer, increased over 3X in 10 years: Analyst

[bit_user]

Yeah the thing with apps not supporting older versions of Android really surprised me at first. I guess I was justused to the pc ecosystem where some companies consider backwards and forwards compatibility to be almost sacrosanct.

Plenty of apps don't support older versions of Windows. For a while, we've seen Win 7 support dropping away. Once MS stops issuing updates for Win 10, I'm sure we'll see software stop support it, as well.

 

[bit_user]

In September of 2023, Intel showed a 20a wafer of Arrow Lake test dies claiming they were on schedule.

https://www.tomshardware.com/news/i...er-with-20a-process-node-chips-arrive-in-2024

Unless that was complete BS at the time, Intel managed to go from we're all good and on schedule to this isn't working, let's cancel 20A and switch to TSMC in one year and released on schedule in October of 2024.

They never said 20A isn't working or hitting performance targets. From what I recall, Gelsinger characterized it more as a "resources" decision, as if he wanted to reallocate some people and equipment currently devoted to 20A over to 18A. I have no idea how accurate or complete that picture was, but they definitely didn't come out and say 20A was broken.

By CPU development standards, that qualifies as last minute.

For sure, but I'm just saying that I think the only way they pulled it off was that Lunar Lake had already done the majority of the work and Arrow Lake just piggybacked off of that.

I also think that this late decision probably meant they got Arrow Lake engineering samples later than they normally would, which could explain why the firmware and driver support was so bad at launch.

 

[The Historical Fidelity]

You're not taking into account die size or yields which dictate wasted silicon. Transistor density is also a moving target that depends entirely on design and what could be shrunk. TSMC's revamped N3 loosened SRAM density to match N5 for gains in other areas. Unfortunately there's no straightforward way to say one node is definitively better than another with regards to cost except a case by case basis.

Some real world density examples based on third party sourced measurements and reported transistor counts:

Apple:
A14 (N5) ~134.1MTr/mm^2
A15 (N5) ~139.3MTr/mm^2
A16 (N4P) ~141.6MTr/mm^2
A17 Pro (N3) ~183MTr/mm^2

AMD:
Zen 4 CCD (N5) ~91. 5MTr/mm^2
Zen 5 CCD (N5 or N4 haven't seen definitive) ~109.2MTr/mm^2

I specifically stated the exact same design, simply ported from N5 to N3, so literally only transistor density of the node is in play and die size, whatever this hypothetical chip was on N5, will be smaller in this instance since any design modification would mean it is not “the exact same design”. And TSMC has stated that it’s N3E D0 defect density is currently at parity with N5 at the same maturity point.

Your Apple A-series density figures are not reliable to estimate since, for all we know, Apple decided to leave dark silicon between transistors to compensate for the limited thermal performance of iPhone sized chassis, for example…

And yes, I used the phrase “napkin math” which means I’m not taking into account every minute detail that may affect the cost per transistor.

However I welcome you to try to estimate the actual die shrink using both the known SRAM and logic densities.

 

[The Historical Fidelity]

Where did you get these two density figures? According to this, N3E only has an advertised density increase of 1.3x over N5:

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https://www.anandtech.com/show/1883...e-power-delivery-in-2026-n2x-added-to-roadmap​

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Also, there seems to be an assumption that N3B is the cheaper node, but N3E sounds like it's the cheaper of the two, and maybe what the $18k figure is citing. Anton characterized N3E as:

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"a relaxed version of N3B, eliminating some EUV layers and completely avoiding the usage of EUV double patterning. This makes it a bit cheaper to produce, and in some cases it widens the process window and yields, though it comes at the cost of some transistor density."​

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Source: https://www.anandtech.com/show/2139...nology-on-track-for-mass-production-this-year​

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Another possible issue is whether you're comparing N5 pricing from the same level of maturity as N3E is currently. I think N5 was almost certainly newer in Q1 of 2020 than N3E is now. That's making N5 look more expensive than it should be, if what we want is an apples-to-apples comparison.

I used the transistor density numbers from Wikichip…like I said…”napkin math”. Also, in one of the TSMC shareholder conference calls, they stated a 1.6x density improvement going from N5 to N3E so the Wikichip numbers jive with their statement. Who knows really though. You asked for an explanation on why I thought transistors are cheaper on N3, so I provided an explanation. Does it mean I am absolutely right? Not at all.

 

[bit_user]

I used the transistor density numbers from Wikichip…

Via the Wayback Machine? For me, wikichip has been inaccessible for about the past 2 weeks. I fear they might be gone forever.

 

[thestryker]

I specifically stated the exact same design, simply ported from N5 to N3, so literally only transistor density of the node is in play and die size, whatever this hypothetical chip was on N5, will be smaller in this instance since any design modification would mean it is not “the exact same design”.

The fact that not everything shrinks at the same rate is the point which is why you can't just use arbitrary numbers to come to any conclusion without knowing the design.

I think the closest chips in design that used different processes would be Intel's Rocket Lake compared to Tiger Lake H. Intel's 10SF had well over double the transistor density of 14nm, but Rocket Lake was nowhere near twice the size.

 

[The Historical Fidelity]

Via the Wayback Machine? For me, wikichip has been inaccessible for about the past 2 weeks. I fear they might be gone forever.

Yeah their servers are shut down for now. Hopefully they are just late on rent. A couple months ago I made snapshots of the TSMC N3 and 5 pages for an argument so I just looked in my phone for them.

 

[The Historical Fidelity]

The fact that not everything shrinks at the same rate is the point which is why you can't just use arbitrary numbers to come to any conclusion without knowing the design.

I think the closest chips in design that used different processes would be Intel's Rocket Lake compared to Tiger Lake H. Intel's 10SF had well over double the transistor density of 14nm, but Rocket Lake was nowhere near twice the size.

Tiger Lake had 2.5x the L2 cache per core, 1.5x the L3 cache, and had a full 96 EU graphics engine in a monolithic die, yeah I’m pretty sure the Rocket Lake die has a lot less transistors on it.

TSMC’s density improvement metric takes all transistors configurations in account. They explained that with a microchip design consisting of 50% Logic, 30% SRAM, and 20% analog circuit, density has been improved by 1.6x going from N5 to N3P.

You are basically demanding an impossible answer…. where in your head, every chip design is a unique snowflake. Which is why you will never be happy with a rule of thumb that fits the situation the majority of the time. There are always exceptions, but we don’t needlessly stress over it.

 

[thestryker]

Tiger Lake had 2.5x the L2 cache per core, 1.5x the L3 cache, and had a full 96 EU graphics engine in a monolithic die, yeah I’m pretty sure the Rocket Lake die has a lot less transistors on it.

Which TGL-H SKU had 96 EUs exactly? At least you're right about the cache though.

They explained that with a microchip design consisting of 50% Logic, 30% SRAM, and 20% analog circuit, density has been improved by 1.6x going from N5 to N3P.

Care to back that up with any evidence? All I've seen regarding sizes is N3E with a 1.6x logic density improvement with 1.3x chip density improvement over N5 and N3P with a 1.04x chip density improvement over N3E.

Really though I don't actually care about a response as this conversation has reached pointlessness I just wanted to correct the incorrect information.

 

[The Historical Fidelity]

Which TGL-H SKU had 96 EUs exactly? At least you're right about the cache though.

Care to back that up with any evidence? All I've seen regarding sizes is N3E with a 1.6x logic density improvement with 1.3x chip density improvement over N5 and N3P with a 1.04x chip density improvement over N3E.

Really though I don't actually care about a response as this conversation has reached pointlessness I just wanted to correct the incorrect information.

Core i7-11320H, 11370H, 11375H, and 11390H from their TigerLake-H35 lineup.

And you are correct, it is 1.3x “mixed chip design” density improvement using the 50% logic-30% SRAM-20% Analog formula N5 to N3E and 1.04x N3E to N3P. Apologies for that mixup.

But my assertion still stands. A 1.3x “mixed chip design” area reduction is greater than the modest 1.06x ($18,000 / $16,988) price increase per wafer. Even at $20,000 a wafer (ie 1.18x price increase) is less than the area reduction.

 

[thestryker]

Core i7-11320H, 11370H, 11375H, and 11390H from their TigerLake-H35 lineup.

I forgot Intel's stupid late generation naming those aren't actually TGL-H they're rebadges of the 11xxGx SKUs with higher power limits. TGL-H was actually a different, larger, die entirely which was 8 core/32 EU.

 

[bit_user]

But my assertion still stands.

You didn't address the point about N3E being more mature (not to mention a cost-reduced node) than N5 was, in the data you cited.

 

[The Historical Fidelity]

I forgot Intel's stupid late generation naming those aren't actually TGL-H they're rebadges of the 11xxGx SKUs with higher power limits. TGL-H was actually a different, larger, die entirely which was 8 core/32 EU.

And I thought AMD’s naming scheme was convoluted… lol

 

[The Historical Fidelity]

You didn't address the point about N3E being more mature (not to mention a cost-reduced node) than N5 was, in the data you cited.

I’ll try and find the source I read where TSMC states N3E has reached D0 defect density parity with N5 at similar maturity points.

 

[Pierce2623]

Plenty of apps don't support older versions of Windows. For a while, we've seen Win 7 support dropping away. Once MS stops issuing updates for Win 10, I'm sure we'll see software stop support it, as well.

Right but nobody still sells Windows 7. People still sell Android 10 and lower products.

 

[Pierce2623]

I forgot Intel's stupid late generation naming those aren't actually TGL-H they're rebadges of the 11xxGx SKUs with higher power limits. TGL-H was actually a different, larger, die entirely which was 8 core/32 EU.

So those were 1165g7 dies and core configurations? I never even knew that. That series through to the 1340p etc is Intel best lineup as far as how competitive it is against the competition .

 

[thestryker]

So those were 1165g7 dies and core configurations? I never even knew that. That series through to the 1340p etc is Intel best lineup as far as how competitive it is against the competition .

Yeah all of the quad core "H" TGL with 96EUs were either B1 or C0 silicon which matched the 11xxGx whereas the actual TGL-H was all R0.