What is memory bank?

[shaharhada]

The notation like 64M×4 means that the memory matrix has 64 million (the product of banks x rows x columns) 4-bit storage locations. There are ×4, ×8, and ×16 DDR chips. The ×4 chips allow the use of advanced error correction features like Chipkill,memory scrubbing and Intel SDDC in server environments, while the ×8 and ×16chips are somewhat less expensive. x8 chips are mainly used in desktops/notebooks but are making entry into the server market. There are normally 4 banks and only one row can be active in each bank.
I don't understand the calculation and how bank is linked to the exercise of the memory matrix?
What is bank?
Is a pattern of bits? If So what its size?
Source:
https://en.wikipedia.org/wiki/DDR_SDRAM

 

[kerberos_20]

DDR RAM is organized in rows or memory pages. The memory pages are divided into four sections, called banks. Each bank has a kind of register associated with it. In order to address a row of DDR RAM (a memory page), one must specify on the pins both a memory bank and a row address. A memory bank can be active, in which case there is an open page associated with the register of the memory bank.

Note that the address lines on the address bus of the CPU will be "wired" to the row address, memory bank, column address and chip select. The address lines can be wired arbitrarily, so that a section of RAM associated with a memory bank may appear to the CPU either to be contiguous or interleaved with other memory banks. Since reading from the same memory bank can be faster, memory banks are generally wired to be contiguous, although it is possible to wire the addresses of different chips as interleaved with each other.

In this example, we assume a 256 Mb chip organized as 32 Meg x 8 (8 data pins), or 8 Meg x 8 data pins x 4 banks. A set of four data bits is specified by using pins A0-A12 for the row address, pins BA0-BA1 for the bank, and pins A0-A9 for the column address. Hence, there are 8K rows, 4 banks, and 1K columns, or 8Kx4x1K=32 Meg of sets of 8 data bits. The row address is specified in a first phase, and the bank and column address is specified in a second phase.