AMD CPU speculation... and expert conjecture

[szatkus]

I have been thinking about the 20 small core fx rumor,So if it's a new architecture with 20 core the single thread performance will be insanely small, but you have all forgotten amd co-developed that threading tech that allows to use many small cores to make 1 big virtual core(the oposite of smt kind of) can't remember what was it called, was quite some time ago but still if that works as good as they promised there may still be a bit of hope(realistically none)

Look at this:
http://ark.intel.com/products/81061/Intel-Xeon-Processor-E5-2699-v3-45M-Cache-2_30-GHz

18 cores at 22nm. So Haswell is small core now?

 

[truegenius]

This does not reflect any of what I am hearing. Honestly...where do you get this stuff? AMD has said nothing of a 20 core CPU...maybe a 20 CU APU. 6-8 serial cores and 12-14 GCN modules....

That would be much closer to what I have heard about APUs down the line....still does not jive with CPU rumors though...

i think that an apu will be better than 20 super slow cores, and that 20 core fx should be a false rumour
in apu side, they can do is die shrink, make 4-6 core core, add more gpu cores, add support for upto 4 channel ddr4 ram (which will be upto board manufacturer to utilize all 4 or use less for different budget board
this way their apu will be capable of 1080p 60fps gaming
currently they have edge over intel in igpu and this is the only way to get much ahead of intel
Intel won't even try to give quad channel, top of the line gpu in 100-200$ price point (apu price range)

i think this hypothetical apu is easily doable (if anyone thinks no then i will want to know why )

 

[truegenius]

^ and on package (not on die) high bandwidth memory like they used to provide in older boards (sideport)

 

[etayorius]

Why the hell AMD has not implemented Quad Channels in Ram? is there some licensing issues or something?

 

[szatkus]

Why the hell AMD has not implemented Quad Channels in Ram? is there some licensing issues or something?

According to wiki AMD was the first one to use quad channel: http://en.wikipedia.org/wiki/Quad-channel_architecture

I guess the reason is the same as always: cost.

 

[cemerian]

Some of you seem surprised by AMD cutting things from their road maps. They are directly in the middle of a transitioning period between Bulldozer and Zen/K12. They are going to cut things. Fottemberg at S|A forums, who has a good history of being right, is calling for 14nm CPUs from AMD to compete with 14nm CPUs from Intel in Q5 2015 or Q1 2016.

The main reason why AMD is canceling products is the lack of funds and their perennial myopie when planing long-term strategy. Being stuck to the 28nm node means that engineers have to look elsewhere to reduce power consumption if want to be barely competitive against Broadwell. Then they rely on stuff such as HDL, and cutting L2 caches to reduce area and power consumption. HDL also reduces frequencies.

As consequence, they cannot use Excavator for APUs above 35W and the previous 45W/65W Carrizo APUs get canceled because would be slower than Kaveri parts. The same reason why Excavator is not coming to FX (AM3+).

There is something interesting about Carrizo that all of us are not paying enough attention. The socket compatibility between Carrizo and Carrizo-L, aka the convergence between Excavator (which is a smaller core than Steamroller) and Puma+ (which is an improved Jaguar).

This seems to confirm that AMD will fuse big and small cores into a single line (K12/Zen). Thus, the new cores will be sized somewhat between both extremes. This means that AMD abandons any pretension to compete with Intel/IBM/ARM-players on big cores. This explains why K12 is targeting dense servers instead high-performance servers, and why Cray didn't select AMD for its future supercomputers.

One has to remember that semicustom/embbeded clients are paying AMD to develop K12/Zen, but those clients don't want big, powerful, and expensive cores; but small, efficient, and cheap cores (Jaguar style).

When Fottemberg said that K12/Zen was being made on TSMC 16nm, I said that was being made on Glofo/Samsung 14nm node (something has been confirmed lately). I will say here that he is being optimist about schedule and that K12 will be not ready before Q1 2016, with Zen coming latter.

Fottemberg contacts said him that AMD prepares 20-core FX CPUs. This confirms that AMD is again trying to hide its deficiency on single thread performance with "moar cores". Most HEDT users will prefer 4/6/8 stronger cores (Skylake) rather than 20 weaker Zen cores.

All points to AMD repeating Bulldozer mistake once again!!!

I have been thinking about the 20 small core fx rumor,So if it's a new architecture with 20 core the single thread performance will be insanely small, but you have all forgotten amd co-developed that threading tech that allows to use many small cores to make 1 big virtual core(the oposite of smt kind of) can't remember what was it called, was quite some time ago but still if that works as good as they promised there may still be a bit of hope(realistically none)

I think you must be referring to this FUD

http://www.theinquirer.net/inquirer/news/1009078/reverse-hyperthreading-exist

There are different academic/industrial attempts to run a single thread on two or more cores and the contributions of AMD to this are easily summarized: zero.

I wrote a recent post about single-thread performance on RWT. I will copy and paste part of it:

VISC (doesn't stand for Virtual Instruction Set Computing). A clustered architecture (up to scheduling) plus internal new ISA optimized for threadlets. Single thread performance follow expected law IPC ~ sqrt(N) with N number of execution cores.

This approach retains usual front-end bottlenecks, doesn't improve branching, and doesn't improve the instruction window, which will limit the wide.

DCE (Dual Core Execution). This approach combines two IOE cores to form a big OOOE core. Head core executes a skeleton of the single thread to provide prefetching and accurate branch prediction for the tail core that runs the full thread. Performance gains are as expected. Up to 200% increase with average of about 41%.

Fusion/Federation. Similar to the last. Two or more simple cores are combined to do a bigger core. However, here the execution model is not runahead but the fused cores work as a monolithic core by combining caches, decoders,... Performance scales similar to monolithic core of the same wide.

TLS (Thread Level Speculation). Breaks a single thread into threadlets that are then run on different cores. Similar to VISC if the split is HW based, but can improve branch prediction via redundant execution. Performance follows the usual square law. On a 64-core [strike]pink unicorn[/strike] manycore, a single thread can be speed up to 8 times.

The last is also known as SpMT (Speculative MultiThreading). In any case, the technologies are not developed enough for commercial usage and the chances that AMD has implemented something similar on Zen are epsilon when epsilon tends to zero.

The most probable implementation for Zen is a traditional CMP superscalar OOOE muarch. I even doubt AMD will implement SMT.

I have been discussing the 20-core FX rumor with Fottemberg and shared with him some math. A 20-core die is compatible with small Zen cores (Jaguar style) having about 40% higher IPC than Jaguar/Piledriver.

no that's not it, i found it luckily here it is http://www.extremetech.com/extreme/192858-visc-cpu-virtual-core-design-emerges-could-this-be-the-conceptual-breakthrough-weve-been-waiting-for

 

[truegenius]

According to wiki AMD was the first one to use quad channel: http://en.wikipedia.org/wiki/Quad-channel_architecture

I guess the reason is the same as always: cost.

i guess it won't be high enough to justify millions of $ getting wasted in R&D every year just to get few % performance increase, and loosing many potential buyers who want 1080p but can't because apu can't do that and loosing those who bought some mid range cards like 265x because they can't pair it with apu, or those customers for whom above 1600mhz ram (taking ddr3 as example) is like a luxary or not available at their location

2 128bit controllers won't even take enough power or die area or won't increase pincount to unmanageable numbers

manufacturing a board with 4 channel support can increase cost by fraction but that will be upto board manufacturer to use all 4 channel or just 2 like now for different price segments board

 

[juanrga]

Fottemberg contacts said him that AMD prepares 20-core FX CPUs. This confirms that AMD is again trying to hide its deficiency on single thread performance with "moar cores". Most HEDT users will prefer 4/6/8 stronger cores (Skylake) rather than 20 weaker Zen cores.

All points to AMD repeating Bulldozer mistake once again!!!

This does not reflect any of what I am hearing. Honestly...where do you get this stuff? AMD has said nothing of a 20 core CPU...maybe a 20 CU APU. 6-8 serial cores and 12-14 GCN modules....

Funny because several months ago we were discussing the 20-core CPU leak using a 20 compute core APU as baseline for the modular approach.

 

[juanrga]

Why the hell AMD has not implemented Quad Channels in Ram? is there some licensing issues or something?

Platform costs and a weak memory controller.

 

[anxiousinfusion]

I change my posts so fast as AMD change the plans.

Initially AMD planned Carrizo on FM2+ as replacement for Kaveri. I posted the old roadmap showing up to 65W Carrizos. That was canceled.

Then AMD planned a Carrizo coming to desktop only in BGA format and up to 35W, with rest of desktop line being covered by a "Kaveri refresh" consisting of higher clocked Kaveris. I have been said that was was canceled as well.

My last info is that "Kaveri refresh" now consists of new models with essentially nothing new beyond minor changes such as firmware fixes. I am said that there is no higher clocks.

I see that Anton Silov claims otherwise. Cannot we just wait and see who is right, Anton or my source?

http://wccftech.com/amd-allegedely-readying-godavari-kaverirefresh-platform-launch-summer-2015/

AMD A10-8850K lifts graphics frequencies by 19 percent against A10-7850K

If true, I don't know who your inside source is but s/he doesn't seem to have very good access to information. Or s/he is adhering strictly to NDA as should be.

 

[blackkstar]

Oh my goodness. Q5 2015? I must be reading too many AMD roadmaps :^) I meant Q4 lol.

In regards, to Hawaii vs GM204, GM204 doesn't scale as well at all

http://www.hardocp.com/article/2014/11/19/nvidia_geforce_gtx_970_sli_4k_nv_surround_review/3#.VMY0eH--TQ0

I'm not normally a fan of [H] but look. On the games where it matters and FPS is no obsurdly high (like Aliens: Isolation), 290x Crossfire is beating out GTX 970 SLI pretty handily, to the point where you're actually enabling extra features with the 290x Crossfire. I can't seem to find a good high resolution review with two GTX 980s in SLI and two 290xs.

I think GTX 900 series is going to have a few months of fame and then be abandoned by all but the "omg AMD drivers are terrible I had a 9700 Pro once and the drivers weren't that great I bet they're still not great I'm not gonna find out give me that delicious 4GB GTX 980* (*3.25GB usable)"

I think some of you have gone off the deep end as concern trolls for AMD. Some of you are right on the money. Part of AMD optimizing R&D money is getting third parties to pay for R&D, and they're doing that.

Honestly, one of the best ways to figure out what AMD's future looks like with Zen would be to get a list of their semi-custom customers and see what sort of demands they would have for products.

 

[juanrga]

I have been thinking about the 20 small core fx rumor,So if it's a new architecture with 20 core the single thread performance will be insanely small, but you have all forgotten amd co-developed that threading tech that allows to use many small cores to make 1 big virtual core(the oposite of smt kind of) can't remember what was it called, was quite some time ago but still if that works as good as they promised there may still be a bit of hope(realistically none)

I think you must be referring to this FUD

http://www.theinquirer.net/inquirer/news/1009078/reverse-hyperthreading-exist

There are different academic/industrial attempts to run a single thread on two or more cores and the contributions of AMD to this are easily summarized: zero.

I wrote a recent post about single-thread performance on RWT. I will copy and paste part of it:

VISC (doesn't stand for Virtual Instruction Set Computing). A clustered architecture (up to scheduling) plus internal new ISA optimized for threadlets. Single thread performance follow expected law IPC ~ sqrt(N) with N number of execution cores.

This approach retains usual front-end bottlenecks, doesn't improve branching, and doesn't improve the instruction window, which will limit the wide.

DCE (Dual Core Execution). This approach combines two IOE cores to form a big OOOE core. Head core executes a skeleton of the single thread to provide prefetching and accurate branch prediction for the tail core that runs the full thread. Performance gains are as expected. Up to 200% increase with average of about 41%.

Fusion/Federation. Similar to the last. Two or more simple cores are combined to do a bigger core. However, here the execution model is not runahead but the fused cores work as a monolithic core by combining caches, decoders,... Performance scales similar to monolithic core of the same wide.

TLS (Thread Level Speculation). Breaks a single thread into threadlets that are then run on different cores. Similar to VISC if the split is HW based, but can improve branch prediction via redundant execution. Performance follows the usual square law. On a 64-core [strike]pink unicorn[/strike] manycore, a single thread can be speed up to 8 times.

The last is also known as SpMT (Speculative MultiThreading). In any case, the technologies are not developed enough for commercial usage and the chances that AMD has implemented something similar on Zen are epsilon when epsilon tends to zero.

The most probable implementation for Zen is a traditional CMP superscalar OOOE muarch. I even doubt AMD will implement SMT.

I have been discussing the 20-core FX rumor with Fottemberg and shared with him some math. A 20-core die is compatible with small Zen cores (Jaguar style) having about 40% higher IPC than Jaguar/Piledriver.

no that's not it, i found it luckily here it is http://www.extremetech.com/extreme/192858-visc-cpu-virtual-core-design-emerges-could-this-be-the-conceptual-breakthrough-weve-been-waiting-for

I thought that you did mean "reverse hyperthreading" because you said "the oposite of smt" and "amd co-developed" it. However, VISC doesn't match that.

VISC is developed by Soft Machines alone. AMD is only one of many other investors funding Soft Machines.

Moreover, VISC is not the opposite of SMT. As mentioned above, VISC is an ordinary cluster architecture, which has been studied in academia/industry during years. The single thread is fetched/decoded and then renamed and issued to each one of the execution clusters (VISC call them 'cores').

Above I explained some of the scaling up limits of VISC.

 

[cemerian]

Ok i made a bit of mistake since i last heard of this quite some time ago and was pretty impressed by it, as to why i pointed to visc is that amd would benefit greatly from would it no(please clarify if i misunderstand it)? after all amd is an investor in it...

 

[etayorius]

New Info on ZEN, Q3 2016 featuring up to 8 Cores:

http://wccftech.com/amd-zen-featured-summit-ridge-family-14nm-processors-rumored-feature-fm3-socket-support-ddr4-memory-compatiblity/

 

[cemerian]

Ok i made a bit of mistake since i last heard of this quite some time ago and was pretty impressed by it, as to why i pointed to visc is that amd would benefit greatly from it, would it not (please clarify if i misunderstand it), but in basics isn't the opposite of hyper threading you are using many small cores to make bigger virtual cores? after all amd is an investor in it...

 

[juanrga]

I change my posts so fast as AMD change the plans.

Initially AMD planned Carrizo on FM2+ as replacement for Kaveri. I posted the old roadmap showing up to 65W Carrizos. That was canceled.

Then AMD planned a Carrizo coming to desktop only in BGA format and up to 35W, with rest of desktop line being covered by a "Kaveri refresh" consisting of higher clocked Kaveris. I have been said that was was canceled as well.

My last info is that "Kaveri refresh" now consists of new models with essentially nothing new beyond minor changes such as firmware fixes. I am said that there is no higher clocks.

I see that Anton Silov claims otherwise. Cannot we just wait and see who is right, Anton or my source?

http://wccftech.com/amd-allegedely-readying-godavari-kaverirefresh-platform-launch-summer-2015/

AMD A10-8850K lifts graphics frequencies by 19 percent against A10-7850K

If true, I don't know who your inside source is but s/he doesn't seem to have very good access to information. Or s/he is adhering strictly to NDA as should be.

I have word that the A10-8850K doesn't exist

http://www.tomshardware.co.uk/forum/352312-28-steamroller-speculation-expert-conjecture/page-351#15126094

My source could be wrong and the Sweclockers/WCCFTECH leak right, but I found that difficult to believe.

First red flag: "Godavari" is the codename of the iGPU on Mullins.
Second red flag: 856MHz is not a valid frequency for Kaveri.
Third red flag: The ratio turbo/base clock is not valid for Kaveri. Moreover increasing the turbo frequency by 100MHz increases the performance by nearly zero percent.
Fourth red flag: Kaveri iGPU is bottlenecked even with unofficial 2400/2600MHz DRAM. Increasing the GPU clocks will increase the bottleneck. What would wait? 5% better gaming FPS?

 

[8350rocks]

The codename for next desktop part is finally leaked...godavari.

That is, indeed, the next desktop series cpu until Zen.

Also, wccftech must have gotten some good info from sweclockers, a lot of that lines up well with what I know.

 

[szatkus]

Original source: http://www.sweclockers.com/nyhet/19954-amd-zen-forst-ut-i-summit-ridge-for-14-nanometer

Sorry, I don't like WCCF's interpretations :>

 

[esrever]

That looks good, if they can pull it off with about the same per core performance as sandybridge, they will be a huge success. Its 8 cores with SMT at 95w, which is lower than the current intel 8 core parts. FM3 is expected as well as the DDR4. I hope everything comes together well, AMD needs a pretty good win on desktop.

 

[szatkus]

That looks good, if they can pull it off with about the same per core performance as sandybridge, they will be a huge success. Its 8 cores with SMT at 95w, which is lower than the current intel 8 core parts. FM3 is expected as well as the DDR4. I hope everything comes together well, AMD needs a pretty good win on desktop.

They need to keep alive for some time. If 380X won't be good they will be dead about year from now.

 

[juanrga]

Ok i made a bit of mistake since i last heard of this quite some time ago and was pretty impressed by it, as to why i pointed to visc is that amd would benefit greatly from it, would it not (please clarify if i misunderstand it), but in basics isn't the opposite of hyper threading you are using many small cores to make bigger virtual cores? after all amd is an investor in it...

TLS (also known as SpMT) is the opposite of SMT (what Intel calls hyperthreading).

As explained before, VISC is built on top of an ordinary clustered architecture. There is no cores, but a set of grouped clusters where each cluster is made of FUs, register file, scheduler unit, and data cache. The clusters are not full cores because lack fetch, decode, branch, and dispatch units, and also lack instruction cache. Soft machines name them cores by marketing purposes.

I also explained before which are the limitations of the approach.

Soft Machines would first finish the R&D, which is already late to Zen, and then sell/license the technology to AMD, if AMD had the money to purchase it.

 

[esrever]

They will be fine for another year or 2 even if they are losing as much as now but they are looking to turn it around this year. The 380x being good will help with that. The 970 vram issue will help AMD clear some existing stock as well even if only slightly.

 

[juanrga]

Original source: http://www.sweclockers.com/nyhet/19954-amd-zen-forst-ut-i-summit-ridge-for-14-nanometer

Sorry, I don't like WCCF's interpretations :>

In this case WCCFTECH simply copied and pasted about word for word.

The Sweclockers report says lots of ordinary stuff: FM3 as replacement for FM2+, DDR4 as replacement for DDR3, 14nm (which was confirmed before), SMT (mentioned at K12 presentation),...

This leaves 95W TPD and the 8-core leak as the only new.

I still have my doubts about SMT, but let us assume the rest is accurate. Max of 95W TDP is current Kaveri top level and I don't consider that HEDT, but mainstream.

8-cores on 95W APU seems to confirm that the cores will be small and efficient rather than big and powerful.

 

[juanrga]

Fottemberg at S|A forums, who has a good history of being right

has said about Sweclokers leaks

I don't think that these leaks are reliable. ^_^

 

[8350rocks]

Original source: http://www.sweclockers.com/nyhet/19954-amd-zen-forst-ut-i-summit-ridge-for-14-nanometer

Sorry, I don't like WCCF's interpretations :>

In this case WCCFTECH simply copied and pasted about word for word.

The Sweclockers report says lots of ordinary stuff: FM3 as replacement for FM2+, DDR4 as replacement for DDR3, 14nm (which was confirmed before), SMT (mentioned at K12 presentation),...

This leaves 95W TPD and the 8-core leak as the only new.

I still have my doubts about SMT, but let us assume the rest is accurate. Max of 95W TDP is current Kaveri top level and I don't consider that HEDT, but mainstream.

8-cores on 95W APU seems to confirm that the cores will be small and efficient rather than big and powerful.

Considering the TDP of Intel's top parts like 4770k, etc...95W on a 14nm process could very well equate to 125W TDP on 32nm process...