[citation][nom]tandemtruths[/nom]This is very much speculation on my part, as I have neither the true experience and knowledge, nor the equipment to verify what I'm about to say. That being said, I have an inkling as to why such a seemingly beautiful architecture can behave in such mediocrity. I first found out about codename Bulldozer a year ago. At that time when discussing to the design profile, AMD referred to the now integer "cores" as integer units inside a physical core. They mentioned the dual pathway multi-threading this design allowed. AMD talked about how this design came into being after noticing Intel's own "Hyperthreading" used a shared pathway on the transistorized core. Now, Intel's "flagmen" do a pretty good job on those single lane roads, that is/was quite evident. AMD, at the time I had initially read up on Bulldozer, said (almost to say that by accident) operating systems would read these integer units as independent cores even though they share an FSB. Multi-threading works by splitting a task, but where does it go when it is prepared? It must be buffered onto an FSB. This is what my theory (though under-equipped) is: Because of the shared FSB1, the integer "cores" bus speed, and thus communication of tasks, is halved if not more so. These integer units also only comprise only half of the transistors per "module", and so are only meant to process smaller task parts. In essence, one could (if this theory has any bearing) say that the advertized clock speed is only behaving at half of it's nominal value. I also have to consider the unholy amount of FSB2 and 3 that could rectify a portion of this loss, and use of multi-threaded applications that don't require very high clock speeds as the individual tasks aren't very intense. However, that would certainly create a throughput bottleneck. My proposition is then this: If AMD could modify the BIOS in such a way as so that the operating system recognizes each "module" as a core instead. With this, the 8000 would be a dual pathway multi-threaded quad core,(as it physically is) the 6000 a multi-threaded triple core, and the 4000 a dual core etc. I believe this would allow for better use of the higher clock speeds for 'handful of intense task' computing that this genre of desktop cpu is mainly called to do. I believe that it would even cut down on power usage as the number of tasks attempting to fit through a small hole are decreased(the fat guy in a little coat issue). That last part I will explain as it sounds like I just pulled it out of my rear. It's a simple "the cable aint big enough for that amount of amps" argument. What happens when you put 600 amps through a 12 gauge wire? It gets HOT. What is heat exactly? I'll give you a hint, in physics class it was always described as being constant. Give up? Energy! Now, when there is such a clog as what I've theorized, it constricts the flow increasing the electron friction. Now there is only one way to calm an excited electron down when it can't move, that is for the atom to give up some of it's energy, again, heat. Think of tasks as gravel. There are some hefty pieces, and there are are small pieces. Multithreaded tasks are small and can fit readily through the small yet many "pipes" of the current 8 core setup. The larger, more intense pieces, need a little electronic Metamucil to get the ball rolling. Now say you have four larger pipes. These pipes also have lanes that organize your gravel better, and they can get those larger pieces through like bad Mexican food. It would be better to have eight pipes if they were the same size, but that takes real estate and also, especially in this case, money. (hence Intel's 990X) My round about point is, it should loose less to waste heat because of the lack of queuing. The best thing about my theory, if true(ish), The performance could be downright amazing. If it keeps up with the 1100t true six core in it's current twisted bowel state, just imagine anywhere from 30% - 60% (those I did pull out of my rear....for science) increase in ability for monolithic computing. Continue to bear in mind (AHHH! there's an ursus in my head!) that this was all developed from an external, third, maybe fourth person perspective. So it's just my two cents. However, it could be two cents from the distant past, valued at two million cents! (that's $20,000!) So you never know...-Andrew[/citation]
as what i said, on the marketing side, they should just count 1 BD module as 1 core with 2 threads, and name the FX-8 as FX-4 (quad cores 8 threads), FX-6 as FX-3(triple cores 6 threads) and FX-4 as FX-2(dual cores 4 threads), set the price of the dual cores 4 threads FX-2 to compete with the i3, and quad cores 8 threads FX-4 to compete with i5, and we will hv the different view at here, so they won't fail that hard, and they can still have times to polish up their fresh new architecture and release another 6 cores 12 threads CPU later to compete with the i7 and their old Phenom II X6