AMD Piledriver rumours ... and expert conjecture

[Reynod]

We have had several requests for a sticky on AMD's yet to be released Piledriver architecture ... so here it is.

I want to make a few things clear though.

Post a question relevant to the topic, or information about the topic, or it will be deleted.

Post any negative personal comments about another user ... and they will be deleted.

Post flame baiting comments about the blue, red and green team and they will be deleted.

Enjoy ...

 

[fazers_on_stun]

So AMD scales using your math and an equal comparison 28% (1.28-1.00) to Intel's -5%(0.95-1.00)

You fail again to comprehend. I used your math, not mine, to come up with 28%. Of course, your math also once calculated the BD die size as bigger than the wafer it was fabbed on , so what can I say..

Anyway, I'm done arguing with someone who for some unknown reason tries to defend any and everything about BD. Your 4100 OC thread failed rather spectacularly so I guess you are trying to make up credibility however you can. Good luck with that.

 

[noob2222]

You fail again to comprehend. I used your math, not mine, to come up with 28%. Of course, your math also once calculated the BD die size as bigger than the wafer it was fabbed on , so what can I say..

Anyway, I'm done arguing with someone who for some unknown reason tries to defend any and everything about BD. Your 4100 OC thread failed rather spectacularly so I guess you are trying to make up credibility however you can. Good luck with that.

Simple logic is your failure to comprhend. No matter what method you use to calculate scaling, amd is roughly 30% higher as long as you treat both sides with the same logic. With that, AMD will respond 30% more as IPC increases, if you can't figure out why that's important, well ...

You can't use different equations and come up an accurate comparison.

Your trying to use compare intel's smt to amd's module, but only doing half the work and calling it good. The only failure is when you were called out, you try to change your own story. Now your reducing youself to tyring insults, way to go.

 

[Chad Boga]

Simple logic is your failure to comprhend. No matter what method you use to calculate scaling, amd is roughly 30% higher as long as you treat both sides with the same logic. With that, AMD will respond 30% more as IPC increases, if you can't figure out why that's important, well ...

You can't use different equations and come up an accurate comparison.

Your trying to use compare intel's smt to amd's module, but only doing half the work and calling it good. The only failure is when you were called out, you try to change your own story. Now your reducing youself to tyring insults, way to go.

You might be surprised at how things turn out.

Taking your example of Cinebench 10

On Cinebench 10, the 2600k's multithreaded score(22,875) is 3.818222 times the score of it's single threaded result(5,991).

BD 8150 has a multithreaded score(20,254) which is 5.1432199 times the score of it's single threaded result(3,938).

So as it stands, on Cinebench 10 multi, the 2600K's advantage over BD 8150 is 12.94%

Now if both Ivy Bridge and PD bring a 10% increase in single threaded performance and their scaling remains as is the case respectively today, this is what happens:

IB Single Score = 6590.1 Multithreaded score = 25,162.46

PD Single Score = 4331.8 Multithreaded score = 22,279.40

Then IB's multithreaded advantage over PD would be 12.94%

 

[Reynod]

Chad's logic looks good to me.

 

[noob2222]

You might be surprised at how things turn out.

Taking your example of Cinebench 10

On Cinebench 10, the 2600k's multithreaded score(22,875) is 3.818222 times the score of it's single threaded result(5,991).

BD 8150 has a multithreaded score(20,254) which is 5.1432199 times the score of it's single threaded result(3,938).

So as it stands, on Cinebench 10 multi, the 2600K's advantage over BD 8150 is 12.94%

Now if both Ivy Bridge and PD bring a 10% increase in single threaded performance and their scaling remains as is the case respectively today, this is what happens:

IB Single Score = 6590.1 Multithreaded score = 25,162.46

PD Single Score = 4331.8 Multithreaded score = 22,279.40

Then IB's multithreaded advantage over PD would be 12.94%

The concept is sound, the math is down and simple, +1 to that, however here is the flaw.

IPC= single core, not module or core+smt. eliminating them from the equasion only eliminates the differences inherent in both architectures. Using the figures above, you are looking at Module scaling vs core+smt scaling.

I will put it this way.

On Cinebench 10, the 2600k's multithreaded (4 core+smt boost) score(22,875) is 3.818222 times (core+smt/4) the score of it's single threaded result(5,991).

BD 8150 has a multithreaded (4 module) score(20,254) which is 5.1432199 times (module/4) the score of it's single threaded result(3,938).

IPC = raw unhindered and unboosted core power (yes BD is low)

Scaling = comparison between 2 architectures.

So, here is the layout

we know I7 2600k scales 9% faster than i5 2500k
We know 8150 scales 34.70196% more efficiently per core than 2600k (5.1432199/3.818222)
We don't know how 8150 scales from 1 thread to 2 within a single module, but that should be easy to obtain, but can estimate its rough value of 34.7% faster than i7 vs i5, wich is 43.7%. ( that actual figure depends greatly on the benchmark being examined, but it works here)



An increase in IPC ... take the same cinebench single thread numbers.
I7 2600k = 5991+10%=6590.1, ok thats done for raw IPC
Now for internal core +smt scaling ... 6590.1+9%= 7249 for core +smt (2 threads)

For 8150, 3938+10%=4331, ok, done for raw IPC
now for internal module scaling. 4331+43.7%=6223 for a module (2 threads)

Now, we didn't increase single core performance on BD compared to SB (both 10%), but on a per module (aka dual thread) vs core+smt, it increased from a deficit of 65.7% to only 85.8% when both processors increased IPC by the same amount.

Now if both Ivy Bridge and PD bring a 10% increase in single threaded performance and their scaling remains as is the case respectively today,

There in lies the problem with your figures, THEIR SCALING ISN'T the same. Module != core+smt.

Edit: your figures are accurate from 1 to 4 threads, past that is where sb will lose ground to BD with IPC improvements.

 

[Chad Boga]

The concept is sound, the math is down and simple, +1 to that, however here is the flaw.

IPC= single core, not module or core+smt. eliminating them from the equasion only eliminates the differences inherent in both architectures. Using the figures above, you are looking at Module scaling vs core+smt scaling.

I will put it this way.

On Cinebench 10, the 2600k's multithreaded (4 core+smt boost) score(22,875) is 3.818222 times the score of it's single threaded result(5,991).

BD 8150 has a multithreaded (4 module) score(20,254) which is 5.1432199 times the score of it's single threaded result(3,938).

IPC = raw unhindered and unboosted core power (yes BD is low)

Scaling = comparison between 2 architectures.

So, here is the layout

we know I7 2600k scales 9% faster than i5 2500k
We know 8150 scales 34.70196% more efficiently per core than 2600k (5.1432199/3.818222)
We don't know how 8150 scales from 1 thread to 2 within a single module, but that should be easy to obtain, but can estimate its rough value of 34.7% faster than i7 vs i5, wich is 43.7%. ( that actual figure depends greatly on the benchmark being examined, but it works here)



An increase in IPC ... take the same cinebench single thread numbers.
I7 2600k = 5991+10%=6590.1, ok thats done for raw IPC
Now for internal core +smt scaling ... 6590.1+9%= 7249 for core +smt (2 threads)

For 8150, 3938+10%=4331, ok, done for raw IPC
now for internal module scaling. 4331+43.7%=6223 for a module (2 threads)

Now, we didn't increase single core performance on BD compared to SB (both 10%), but on a per module (aka dual thread) vs core+smt, it increased from a deficit of 65.7% to only 85.8% when both processors increased IPC by the same amount.

Now if both Ivy Bridge and PD bring a 10% increase in single threaded performance and their scaling remains as is the case respectively today,

There in lies the problem with your figures, THEIR SCALING ISN'T the same. Module != core+smt

You are taking two bites of the cherry here.

BD's 5.1432199 speed up from single thread to multi-thread includes Module scaling.

You want to add on an additional 43.7% that just won't show up.

 

[noob2222]

you inlcluded it INTO THE SINGLE THREAD so that IPC = module or Core+smt /2, wich IPC is not.

simply dividing totals doesn't remove inside scaling. instead it makes them = to each other (50% for both) and they definately are not.

Think about it this way, IPC = single thread performance aka a core

SMT as stated by Intel boosts single thread performance by "30%"

So does that mean a core + smt = IPC +30% where single threaded performance is a constant (5991)
or is it core +smt = (ipc +30%)/2 =5991 where single threaded performance (ipc) will adjust itself when you turn smt on or off

 

[-Fran-]

IPC = Instructions per clock != Single Threaded Performance. Period.

IPC is a whole metric by itself that's not affected by the way a single core distributes it's resources on the cycles. So, if you ask me, an HT capable core has more IPC than a non active HT one per sé. Marketing and bluff/BS on the other side, well, that's really messing people's mind from the simple stuff.

My 2 cents to your interesting discussion.

Cheers!

 

[jdwii]

you inlcluded it INTO THE SINGLE THREAD so that IPC = module or Core+smt /2, wich IPC is not.

simply dividing totals doesn't remove inside scaling. instead it makes them = to each other (50% for both) and they definately are not.

Think about it this way, IPC = single thread performance aka a core

SMT as stated by Intel boosts single thread performance by "30%"

So does that mean a core + smt = IPC +30% where single threaded performance is a constant (5991)
or is it core +smt = (ipc +30%)/2 =5991 where single threaded performance (ipc) will adjust itself when you turn smt on or off

I don't understand what your saying are you saying if software scales 100% perfect to 8 cores that's when BD will beat Sandy. As it stand now even Hand brake a program that scales perfectly to 8 cores is faster on a I72600K or they are the same speed. But when you do any gaming that uses 4 cores or less BD will get creamed. Even if you use a program that can use 6 cores Sandy should still be faster. At least that's what where seeing.

 

[fazers_on_stun]

FYI, S/A has an interview with JF-AMD dated yesterday: http://semiaccurate.com/2011/11/09/a-walk-through-amds-server-marketplace/

So it doesn't look like he got laid off.

Also, it appears we will have to wait for AMD's next financial meeting before we find out what new direction AMD is planning to take - the project WIN thing was just an internal announcement about the layoffs that Read made yesterday.:

http://www.anandtech.com/show/5079/amds-project-win-a-misunderstanding

 

[noob2222]

I don't understand what your saying are you saying if software scales 100% perfect to 8 cores that's when BD will beat Sandy. As it stand now even Hand brake a program that scales perfectly to 8 cores is faster on a I72600K or they are the same speed. But when you do any gaming that uses 4 cores or less BD will get creamed. Even if you use a program that can use 6 cores Sandy should still be faster. At least that's what where seeing.

pretty close. SB scales very well up to its "core" count, then drops off drastically

BD scales up to its module count and drops off much slower than SB.

http://www.phoronix.com/scan.php?page=article&item=amd_bulldozer_scaling&num=5

Notice how 980x drops off the cliff at 6 to 8 threads, sometimes resulting in slower than before

BD does not suffer that same brick wall, so if they can boost IPC, then that boost is all the way across, not just to the brick wall of smt where the benefit from ipc dissappears.

 

[gamerk316]

^^ Of course BD modules scale better; HTT is only about 20% efficent, and CMT is about 80% efficent. Therefore, BD scales better after all its normal cores are used. Problem is, CMT takes a LOT more die space...For the space it uses, HTT is actually quite effective.

Although its funny we're doing a module to core comparison again...thought that argument was already put to rest.

 

[noob2222]

IPC = Instructions per clock != Single Threaded Performance. Period.

IPC is a whole metric by itself that's not affected by the way a single core distributes it's resources on the cycles. So, if you ask me, an HT capable core has more IPC than a non active HT one per sé. Marketing and bluff/BS on the other side, well, that's really messing people's mind from the simple stuff.

My 2 cents to your interesting discussion.

Cheers!

For all intensive purposes, IPC itself is pointless and cannot be measured because its influenced by every aspect of the cpu, clock gen, missed cycles, fast/slow caches speeds, any and all bugs, ect.

Second, intel and AMD both have stated ipc increases in % .. if you try to make that actual ipc, 4 per clock, that means 10% will now be 4.4 instructions per clock ... For all IPC relate talk, its discussing bringing Actual IPC closer to theoretical 4 per clock. Wich is currently measured by single threaded benchmarks.

In short, old school IPC of the 8088 era is dead.

The number of instructions executed per clock is not a constant for a given processor; it depends on how the particular software being run interacts with the processor, and indeed the entire machine, particularly the memory hierarchy.

 

[jimmysmitty]

FYI, S/A has an interview with JF-AMD dated yesterday: http://semiaccurate.com/2011/11/09/a-walk-through-amds-server-marketplace/

So it doesn't look like he got laid off.

Also, it appears we will have to wait for AMD's next financial meeting before we find out what new direction AMD is planning to take - the project WIN thing was just an internal announcement about the layoffs that Read made yesterday.:

http://www.anandtech.com/show/5079/amds-project-win-a-misunderstanding

How do you call layoffs project WIN? If anything its a FAIL to those who are now jobless in an already rough job market.

 

[-Fran-]

For all intensive purposes, IPC itself is pointless and cannot be measured because its influenced by every aspect of the cpu, clock gen, missed cycles, fast/slow caches speeds, any and all bugs, ect.

Second, intel and AMD both have stated ipc increases in % .. if you try to make that actual ipc, 4 per clock, that means 10% will now be 4.4 instructions per clock ... For all IPC relate talk, its discussing bringing Actual IPC closer to theoretical 4 per clock. Wich is currently measured by single threaded benchmarks.

In short, old school IPC of the 8088 era is dead.

The number of instructions executed per clock is not a constant for a given processor; it depends on how the particular software being run interacts with the processor, and indeed the entire machine, particularly the memory hierarchy.

Uhm... Not quite... In fact you move things around inside a CPU (a core) per clock, so you actually know how much "work" you get done. That the theory side of it, off course.

It's just that's really hard to do so from outside. It's like quantum physics when measuring electrons, but just a tad simplified, lol.

Anyway, my point wasn't about discussing how you measure it, because you're right there, since there's no other meaningful way to do so. Just don't get buffled by marketing names and traits. A BD module or an HT capable core are the same thing in it's essence: a monolithic CPU that distributes things given an instruction per clock. We can argue some more about it, but I'll give BD the benefit of doubt thanks to it's weird ass approach that 1 module = 2 cores, but you know that when an instruction comes in it's "the module" that knows what to do with it (way simplified, but oh well).

Cheers!

 

[homefellas87]

It seems as if an eternity has passed since the excitement around AMD's Hammer technology took feverish hold of enthusiasts. However, the discussion has often been marred or confused by the fact that the all-embracing term Hammer applied to two completely different products - Clawhammer, and Seldgehammer.

 

[homefellas87]

It seems as if an eternity has passed since the excitement around AMD's Hammer technology took feverish hold of enthusiasts. However, the discussion has often been marred or confused by the fact that the all-embracing term Hammer applied to two completely different products - Clawhammer, and Seldgehammer.

 

[Reynod]

FYI, S/A has an interview with JF-AMD dated yesterday: http://semiaccurate.com/2011/11/09/a-walk-through-amds-server-marketplace/

So it doesn't look like he got laid off.

Also, it appears we will have to wait for AMD's next financial meeting before we find out what new direction AMD is planning to take - the project WIN thing was just an internal announcement about the layoffs that Read made yesterday.:

http://www.anandtech.com/show/5079/amds-project-win-a-misunderstanding

I am glad John did ok ... personally I like the guy and hopes he comes back here.

Look I apologise to 384-bit and those of you whose posts I culled a bit indiscriminately but I needed to respond quickly ... and i hope you understand.

I'd like John to spend more time in the server area we recently setup and try to get more of you with experience in servers to contribute as well.

Servers are not something I know a lot about ... I can't get my head around some of the benchmarks ... so I struggle giving people advice in that regard.

 

[fazers_on_stun]

How do you call layoffs project WIN? If anything its a FAIL to those who are now jobless in an already rough job market.

LOL - probably the same PR people who (1) didn't get laid off, and (2) advertise the 8150 as a huge gaming CPU or some such 😀. I guess in the PR world, making pigs fly is a job requirement 😛..

 

[fazers_on_stun]

I am glad John did ok ... personally I like the guy and hopes he comes back here.

Look I apologise to 384-bit and those of you whose posts I culled a bit indiscriminately but I needed to respond quickly ... and i hope you understand.

I'd like John to spend more time in the server area we recently setup and try to get more of you with experience in servers to contribute as well.

Servers are not something I know a lot about ... I can't get my head around some of the benchmarks ... so I struggle giving people advice in that regard.

Yeah, I think he got hammered in various forums a bit unfairly, but at least not here in THG that I saw. If there were such posts, I hope they got deleted quickly.

I too would like to see him come back and participate.

Didn't that server section get set up with a request from Upendra09 a year or so ago?? Kinda funny since he said he didn't know anything about them at the tme 😛.. Or maybe it was our illustrious Dogman - I forget which..

 

[jdwii]

For all intensive purposes, IPC itself is pointless and cannot be measured because its influenced by every aspect of the cpu, clock gen, missed cycles, fast/slow caches speeds, any and all bugs, ect.

Second, intel and AMD both have stated ipc increases in % .. if you try to make that actual ipc, 4 per clock, that means 10% will now be 4.4 instructions per clock ... For all IPC relate talk, its discussing bringing Actual IPC closer to theoretical 4 per clock. Wich is currently measured by single threaded benchmarks.

In short, old school IPC of the 8088 era is dead.

The number of instructions executed per clock is not a constant for a given processor; it depends on how the particular software being run interacts with the processor, and indeed the entire machine, particularly the memory hierarchy.

IPC means instructions per cycle A lot of people including my self once did not know that even IPC is limited to software scaling. What Instruction is being used to calculate performance on a Processor what about other Instructions such as AVX or AES. What would you say if i thought CPI(Cycles per instruction) is more important then IPC?

 

[jdwii]

LOL - probably the same PR people who (1) didn't get laid off, and (2) advertise the 8150 as a huge gaming CPU or some such 😀. I guess in the PR world, making pigs fly is a job requirement 😛..

Funny, By the way does anyone else thank A CEO should make 1M a year When their company is worth less then it was 6 months ago?

 

[dogman_1234]

Yeah, I think he got hammered in various forums a bit unfairly, but at least not here in THG that I saw. If there were such posts, I hope they got deleted quickly.

I too would like to see him come back and participate.

Didn't that server section get set up with a request from Upendra09 a year or so ago?? Kinda funny since he said he didn't know anything about them at the time 😛.. Or maybe it was our illustrious Dogman - I forget which..

I have no clue what you are talking about...but okay...

 

[fazers_on_stun]

Funny, By the way does anyone else thank A CEO should make 1M a year When their company is worth less then it was 6 months ago?

$1M seems like small potatoes compared to some other CEO salaries. IIRC Hector Ruiz (AMD's CEO before Dirk Meyer) got around $15M in salary, options & bonuses, and if anybody could be said to have driven AMD nearly to bankruptcy, it was him. Steve Jobs only got $1 or maybe $10 a year as CEO of Apple, but he had a ton of stock options. IIRC he never gave to charity (at least nowhere near the scale of, say Bill Gates who has given over $10 billion to date). He also didn't believe in daily bathing or deodorant from what I've read - maybe Apple should have forced more $$ on him so he could buy toiletries 😛.

There was a rumor about Read just being a caretaker CEO to stand in while the BoD looked to find a buyer for AMD. I doubt that, but we should see something about where AMD is headed during the financial meeting sometime in January.

 

[fazers_on_stun]

I have no clue what you are talking about...but okay...

OK - it was you who wanted to start his own CPU company, and Uppity who wanted to start a server section.

Looks like Uppity won the race 😀..