what!? i remember reading about that '5% share' in servers in an article... but that's a steep drop imo. aren't servers the biggest revenue generating sector like office pcs?
Yeah, the margins are huge in comparison to any other segment. IIRC AMD was getting over $1K for the higher-end Magny Cours, and of course for dual or quad-sockets that's 2 or 4 CPUs sold for each one...
What's funny is that right before the 12-core multi-chip module MC was released about 2 years ago, AMD had over 12% of the server market, but then started dropping when the 6-core/12-thread Westmere Xeons appeared about the same time. MC was delayed too IIRC, so basically AMD squandered yet another opportunity to take away marketshare from Intel by having the top end to itself. As Reid says, execution is pretty important..
glofo's early difficulty in producing sufficient amount of llano apus held back amd from gaining an even bigger share in notebook market. i'd rather credit tsmc for the majority of apus' success.
this is one of the factors amd-favoring people here have been avoiding... trinity's biggest weakness isn't performance at all, it is wide availability. apus can earn huge profits in markets like china, india but they'll have to be available. if the yields are not enough.....
take any assurance about trinity yields from amd with a grain of salt.
Supposedly the Llano & BD problems, delays and initial low yields were due to moving the GPU from strained silicon to SOI, requiring a redesign of the layout. I'd bet it was more complicated than that - GF had never done HKMG before, and they went with IBM's gate-first version which requires the Hafnium compound to be able to withstand the annealing temperatures (around 1000 degrees). In contrast, Intel & TSMC's gate-last approach use dummy gates for self-alignment, then replaces them with the HKMG gate after the annealing process, so the parameters can be 'tuned' for performance rather than surviving high temps. This would somewhat explain why BD uses too much power as well, since HKMG is supposed to reduce leakage by 30% or more.
Supposedly gate-first has up to 20% more density than gate last, but you can't tell that from BD's huge die size (or the missing 600 million transistors
😛).
So new designs on a major new process node = 2X potential problems. Which is why Intel does the tick-tock, to minimize risks.
Llano was delayed by at least 9 months and BD probably by an equal amount if not more. I don't believe TSMC does SOI, so AMD is pretty much stuck with GloFlo I guess. If Trinity doesn't appear until Q4, then I'd say GF's problems continue to some extent. They are switching to gate-last at 22nm, but who knows when they'll get to that node..