I think DDR6 is going in the "Half-Right" direction.FWIW, DDR5 halved the channel width and DDR6 is set to do it again. Your explanation is consistent with that, so I'll credit you with maybe having a good point. I hope you're right.
Yes, they want Quad DIMM MSC (Memory Sub-Channels).
Instead of 2x MSC's like DDR5 with Memory Channel A & B, they're going with Memory Channel A & B on one side, C & D on the other side.
I think that is the logical natural progression, from 2 MSC's to 4 MSC's
Splitting the Bandwidth in half is what I don't think is a good idea.
The current DDR5 Channel Bandwidth of 32-bit/40-bit is fine as is.
They just need to increase the Pin-Count and keep the channel width the same.
Yes, that will double the Pin-Count, but so be it.
At some points, you got to stop letting them lower the Channel Width and just start increasing Frequency along with the Channel Width.
We went from 64-bit down to 32-bit from DDR1/2/3/4 -> DDR5.
We should stick with 32-bit for a few generations before we consider lowering the Channel Width.