AMD to integrate PCIe into CPU

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

AMD to integrate PCIe
http://www.theinquirer.net/?article=24756

Yousuf Khan

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Wireless, sound, IDE/SATA, USB/Firewire. Too many features that just
don't deserve a piece of the CPU real-estate, and don't really need the
full speed of the CPU to be dedicated to them. Just a CPU and a
southbridge basically. Just one step removed from a SOC.

Other things I see them possibly using the integrated PCI-e connector
for is integrated shared memory video. They can use the PCI-e video
protocols to share memory with the integrated video chipset directly.

Another use would be to offer even faster full dual-x16 SLI/Crossfire
support. They can connect one high-end video card to a northbridge x16
connector while the other one uses the CPU's x16 connector.

On the server front, they can connect things like commodity PCI-e
Infiniband cards directly to the CPU for HPC clusters.

Yousuf Khan

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

YKhan wrote:
>
> On the server front, they can connect things like commodity PCI-e
> Infiniband cards directly to the CPU for HPC clusters.
>
LOM..."Landed-on-motherboard" more likely.

RM

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Robert Myers wrote:
> YKhan wrote:
> >
> > On the server front, they can connect things like commodity PCI-e
> > Infiniband cards directly to the CPU for HPC clusters.
> >
> LOM..."Landed-on-motherboard" more likely.

No, that is already done now, through Hypertransport. But built-in
Infiniband would be a very specialized requirement. That would make it
a very specialized subcategory of an already specialized subcategory.
Can't see the economies of scale being all that good for a motherboard
with built-in Infiniband. This way they can plug a bog-standard PCIe
Infiniband adapter (as bog-standard as those things get anyways), and
get slightly better latency out of it. May not be as good as
motherboard Infiniband, but better than through a chipset PCIe
connector.

Yousuf Khan

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Wed, 20 Jul 2005 07:58:35 -0700, YKhan wrote:

> AMD to integrate PCIe
> http://www.theinquirer.net/?article=24756
>
> Yousuf Khan

Two thoughts occur first that motherboards are about to get a fair bit
cheaper and second that overclocking is about to get more complex.

sounds like motherboards are basicly going to get turned into sockets and
a few things that wouldn't work inside the cpu. im sure ive read somewhere
that wireless and sound will need to remain seperate due to the way they
work.

 

[mygarbage2000]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Wed, 20 Jul 2005 18:12:37 GMT, epaton <epaton@null.com> wrote:

>On Wed, 20 Jul 2005 07:58:35 -0700, YKhan wrote:
>
>> AMD to integrate PCIe
>> http://www.theinquirer.net/?article=24756
>>
>> Yousuf Khan
>
>Two thoughts occur first that motherboards are about to get a fair bit
>cheaper and second that overclocking is about to get more complex.
>
>sounds like motherboards are basicly going to get turned into sockets and
>a few things that wouldn't work inside the cpu. im sure ive read somewhere
>that wireless and sound will need to remain seperate due to the way they
>work.
>
Poor VIA, SIS, and ULI - they will be relegated to making commodity
south bridges, or fight mighty Intel for a piece of Pentium chipset
market. Nvidia and ATI have at least something to fall back on -
graphics. High end GPU will stay separate from CPU at least for quite
a while. OTOH, low end GPU may find its way into south bridges,
making them a bit less of a cheap commodity.

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

nobody@nowhere.net wrote:
> Poor VIA, SIS, and ULI - they will be relegated to making commodity
> south bridges, or fight mighty Intel for a piece of Pentium chipset
> market. Nvidia and ATI have at least something to fall back on -
> graphics. High end GPU will stay separate from CPU at least for quite
> a while. OTOH, low end GPU may find its way into south bridges,
> making them a bit less of a cheap commodity.
>

Considering the cooling requirements of even a low-end GPU (cooling fins
coming out all over the place), it's unlikely that they'll try to
integrate the GPU with the southbridge. The video chip overheats and you
lose connection to your hard drives? 🙂

Yousuf Khan

 

[mygarbage2000]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Fri, 22 Jul 2005 08:38:58 -0400, Yousuf Khan <bbbl67@ezrs.com>
wrote:

>nobody@nowhere.net wrote:
>> Poor VIA, SIS, and ULI - they will be relegated to making commodity
>> south bridges, or fight mighty Intel for a piece of Pentium chipset
>> market. Nvidia and ATI have at least something to fall back on -
>> graphics. High end GPU will stay separate from CPU at least for quite
>> a while. OTOH, low end GPU may find its way into south bridges,
>> making them a bit less of a cheap commodity.
>>
>
>Considering the cooling requirements of even a low-end GPU (cooling fins
>coming out all over the place), it's unlikely that they'll try to
>integrate the GPU with the southbridge. The video chip overheats and you
>lose connection to your hard drives? 🙂
>
> Yousuf Khan

Low end GPU like X300 can do with passive heatsink, and quite a few
north bridges now need a fan even without graphics. So they'll slap a
fan on the south bridge/GPU combo. If a fan is not enough a BIG fan
will do. After all they'll need to sell something, and the market for
cheap integrated chipsets will always be there. Looks like nobody at
Intel is afraid to lose connection to RAM because the integrated
Extreme Graphics could overheat ;-)

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

nobody@nowhere.net wrote:
> Low end GPU like X300 can do with passive heatsink, and quite a few
> north bridges now need a fan even without graphics. So they'll slap a
> fan on the south bridge/GPU combo. If a fan is not enough a BIG fan
> will do. After all they'll need to sell something, and the market for
> cheap integrated chipsets will always be there. Looks like nobody at
> Intel is afraid to lose connection to RAM because the integrated
> Extreme Graphics could overheat ;-)
>

One thing nobody has mentioned yet is the shear irony of this situation.
Intel created PCI-e as a competitor to Hypertransport, because they
refused to adhere to a standard that AMD came up with. AMD gave the
green light to PCI-e without even a fight, knowing full well that PCI-e
and HT would be compatible with each other (just slightly different
physical layers), and now it may come up with the first PCI-e integrated
into the CPU.

Yousuf Khan

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Perhaps this will remind you?

Approval near on Intel PC-overhaul plan | CNET News.com
http://news.com.com/2100-1001-270823.html

Yousuf Khan

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Yousuf Khan wrote:
> nobody@nowhere.net wrote:
>
>> Low end GPU like X300 can do with passive heatsink, and quite a few
>> north bridges now need a fan even without graphics. So they'll slap a
>> fan on the south bridge/GPU combo. If a fan is not enough a BIG fan
>> will do. After all they'll need to sell something, and the market for
>> cheap integrated chipsets will always be there. Looks like nobody at
>> Intel is afraid to lose connection to RAM because the integrated
>> Extreme Graphics could overheat ;-)
>>
>
> One thing nobody has mentioned yet is the shear irony of this situation.
> Intel created PCI-e as a competitor to Hypertransport, because they
> refused to adhere to a standard that AMD came up with. AMD gave the
> green light to PCI-e without even a fight, knowing full well that PCI-e
> and HT would be compatible with each other (just slightly different
> physical layers), and now it may come up with the first PCI-e integrated
> into the CPU.
>
> Yousuf Khan

Sigh. where do you guys get these fairy stories? PCI-E was invented as
an IO expansion network to replace pci-x which was reaching the end of
its rope and took too many pins. InfiniBand was too server oriented.

Is everybody in this group full of conspiracy theories? I am really
starting to wonder about you guys.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

YKhan wrote:
> Perhaps this will remind you?
>
> Approval near on Intel PC-overhaul plan | CNET News.com
> http://news.com.com/2100-1001-270823.html
>
> Yousuf Khan
>

Yes, it says intel got pci-e adopted. Hypertransport is totally
different thing, capable of driving a few inches. It is a FSB. Why the
doof that wrote the article even mentioned it isn't clear.



--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Del Cecchi wrote:
> YKhan wrote:
>
>> Perhaps this will remind you?
>>
>> Approval near on Intel PC-overhaul plan | CNET News.com
>> http://news.com.com/2100-1001-270823.html
>>
>> Yousuf Khan
>>
>
> Yes, it says intel got pci-e adopted. Hypertransport is totally
> different thing, capable of driving a few inches. It is a FSB. Why the
> doof that wrote the article even mentioned it isn't clear.
>

Because there was a time when HT was proposed as the next generation
PCI. It was initially going to allow PCI to get faster by simply
splitting each PCI slot into its own PCI bus, with each of the PCI buses
connected over HT. Then eventually they were talking about HT gaining
its own slot connector and people using HT directly.

Both of those scenarios actually did come true, in a way. HT has become
a very popular underlying layer for PCI, PCI-X and even PCI-E. There is
also a slot connector standard for HT called HTX, but it's not
necessarily all that popular.

Yousuf Khan

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sun, 24 Jul 2005 18:29:14 -0400, Yousuf Khan <bbbl67@ezrs.com>
wrote:
>Del Cecchi wrote:
>> Yes, it says intel got pci-e adopted. Hypertransport is totally
>> different thing, capable of driving a few inches. It is a FSB. Why the
>> doof that wrote the article even mentioned it isn't clear.

There's no spec that shows exactly how far each could be driven, but I
suspect that you'll find Hypertransport and PCI-Express could achieve
comparable distances for similar data rates. My idea of "a few
inches" in computer designs is 2-3", and there are definitely HT
setups running at high data rates that go further than that (I would
guess that the furthest I've seen would be about 12" for a 16-bit,
2000MT/s link).

>Because there was a time when HT was proposed as the next generation
>PCI. It was initially going to allow PCI to get faster by simply
>splitting each PCI slot into its own PCI bus, with each of the PCI buses
>connected over HT. Then eventually they were talking about HT gaining
>its own slot connector and people using HT directly.
>
>Both of those scenarios actually did come true, in a way. HT has become
>a very popular underlying layer for PCI, PCI-X and even PCI-E. There is
>also a slot connector standard for HT called HTX, but it's not
>necessarily all that popular.

To the best of my knowledge there is only ONE HTX add-in card, an
Infiniband card from Pathscale. This card was recently used to set
some world records for low-latency communication in clusters.

The slot is actually VERY similar to PCI-Express (same physical
connectors) and the specs are designed to make it easy to have both
PCI-E and HTX on the same board.

Really when you get right down to it, Hypertransport and PCI-Express
started out with rather different goals but the end result is
surprisingly similar. I guess there really are only so many ways to
skin a cat.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Yousuf Khan wrote:
> Del Cecchi wrote:
> > HT can go maybe a foot, if you are really lucky. Work out the skew
> > budgets. At 2000 MT, the board is allocated less than 100 ps as I recall.
> >
> > PCI-E on the other hand can go several meters.
> >
> > Totally different approaches.
>
> Which is why PCI-e never got adopted as a CPU to CPU interconnect.
>
> Yousuf Khan

One never knows what the future holds. Anyway, it's pretty obvious
that parallel transmission (read HT) is the way of the past. If you
look at any high performance interconnect, they are all serial. Talk
to the Rambus guys, they know what they are doing...

Now, as to whether serial connections between CPUs is a good idea, I am
not entirely sure; I suspect Del is far more qualified to discuss that
topic than I am. Generally, serial connections can be driven far
faster, but there is slighly longer latency for SERDES.

HT was never envisioned to replace PCI-X, PCI or anything else.
Yousuf, you should at least try to distinguish yourself from AMD PR
personnel...

David

 

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Tony Hill wrote:
> On Sun, 24 Jul 2005 18:29:14 -0400, Yousuf Khan <bbbl67@ezrs.com>
> wrote:
>
>>Del Cecchi wrote:
>>
>>>Yes, it says intel got pci-e adopted. Hypertransport is totally
>>>different thing, capable of driving a few inches. It is a FSB. Why the
>>>doof that wrote the article even mentioned it isn't clear.
>
>
> There's no spec that shows exactly how far each could be driven, but I
> suspect that you'll find Hypertransport and PCI-Express could achieve
> comparable distances for similar data rates. My idea of "a few
> inches" in computer designs is 2-3", and there are definitely HT
> setups running at high data rates that go further than that (I would
> guess that the furthest I've seen would be about 12" for a 16-bit,
> 2000MT/s link).
>
>
>>Because there was a time when HT was proposed as the next generation
>>PCI. It was initially going to allow PCI to get faster by simply
>>splitting each PCI slot into its own PCI bus, with each of the PCI buses
>>connected over HT. Then eventually they were talking about HT gaining
>>its own slot connector and people using HT directly.
>>
>>Both of those scenarios actually did come true, in a way. HT has become
>>a very popular underlying layer for PCI, PCI-X and even PCI-E. There is
>>also a slot connector standard for HT called HTX, but it's not
>>necessarily all that popular.
>
>
> To the best of my knowledge there is only ONE HTX add-in card, an
> Infiniband card from Pathscale. This card was recently used to set
> some world records for low-latency communication in clusters.
>
> The slot is actually VERY similar to PCI-Express (same physical
> connectors) and the specs are designed to make it easy to have both
> PCI-E and HTX on the same board.
>
> Really when you get right down to it, Hypertransport and PCI-Express
> started out with rather different goals but the end result is
> surprisingly similar. I guess there really are only so many ways to
> skin a cat.
>
> -------------
> Tony Hill
> hilla <underscore> 20 <at> yahoo <dot> ca


HT can go maybe a foot, if you are really lucky. Work out the skew
budgets. At 2000 MT, the board is allocated less than 100 ps as I recall.

PCI-E on the other hand can go several meters.

Totally different approaches.

del

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Tony Hill wrote:
>>Both of those scenarios actually did come true, in a way. HT has become
>>a very popular underlying layer for PCI, PCI-X and even PCI-E. There is
>>also a slot connector standard for HT called HTX, but it's not
>>necessarily all that popular.
>
>
> To the best of my knowledge there is only ONE HTX add-in card, an
> Infiniband card from Pathscale. This card was recently used to set
> some world records for low-latency communication in clusters.
>
> The slot is actually VERY similar to PCI-Express (same physical
> connectors) and the specs are designed to make it easy to have both
> PCI-E and HTX on the same board.

I didn't realize that PCI-E and HTX had similar connectors. Is one an
extension of the other (eg. HTX is a few extra slots beyond the PCIE
slots, like VESA was compared to ISA), or something like EISA was to
ISA, with somewhat deeper slots? Or are they totally incompatible but
they look similar?

> Really when you get right down to it, Hypertransport and PCI-Express
> started out with rather different goals but the end result is
> surprisingly similar. I guess there really are only so many ways to
> skin a cat.

Yup.

Yousuf Khan

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Del Cecchi wrote:
> HT can go maybe a foot, if you are really lucky. Work out the skew
> budgets. At 2000 MT, the board is allocated less than 100 ps as I recall.
>
> PCI-E on the other hand can go several meters.
>
> Totally different approaches.

Which is why PCI-e never got adopted as a CPU to CPU interconnect.

Yousuf Khan

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

David Kanter wrote:
> One never knows what the future holds. Anyway, it's pretty obvious
> that parallel transmission (read HT) is the way of the past. If you
> look at any high performance interconnect, they are all serial. Talk
> to the Rambus guys, they know what they are doing...

Not quite, HT is a set of multiple serial interfaces. You can go from
one to 16 unidirectional links, one to 16 in the other direction too.
Exactly the same as PCI-e.

> HT was never envisioned to replace PCI-X, PCI or anything else.
> Yousuf, you should at least try to distinguish yourself from AMD PR
> personnel...

It would be much easier if I didn't have to go around correcting
misinformation.

Yousuf Khan

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

> While a serial (and encoded) link is way easier to handle, the sky is
> not the limit. Consider that at 10Gb/s standard FR-4 board material
> have quite frightening losses, which limits the length you can send
> it. The several meters that Del talk about is on cables, I think.

I don't really know anything about board engineering, but I think that
one thing we might want to consider is that in the near future some CPU
interconnects will simply be on-die; and you can afford to have
ridiculously fast and nice interconnects there.

Also, does PCB have worse loss than cables, as that's what you seem to
be implying.

> And just exactly why would you want to go several meters on a CPU to
> CPU interconnect (at least in the x86 mass-market)?
>
> Sure, the parallel link as other problems, also pointed out by Del,
> but my point here is that blindly claiming that either technology is
> the "right thing" is not a good idea.
>
> Latency, bandwidth, die area, power consumption, and maximum trace
> length should all be considered.

Absolutely, and for a CPU interconnect you probably end up sacrificing
the latter. But as I understand, serial encoding schemes can have a
very small difference in latency from a parallel one (when designed
properly).

> > Now, as to whether serial connections between CPUs is a good idea, I am
> > not entirely sure; I suspect Del is far more qualified to discuss that
> > topic than I am. Generally, serial connections can be driven far
> > faster, but there is slighly longer latency for SERDES.
>
> Definitely - and as we know: money can buy you bandwidth, but latency
> is forever.

Hehehe. We should start selling latency to compete with diamonds,
maybe we can piggyback off of all those De Beers commercials...

> Think of the performace of SDRAMs - while the DDR's have awesome peak
> BW numbers, they rarely translate into real-world benefits that is
> worth taking about.

CPU's always need more bandwidth though, and I think the benefits are
pretty obvious, especially when you start talking about servers with
multiple processors.

David

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Yousuf Khan wrote:
> David Kanter wrote:
> > One never knows what the future holds. Anyway, it's pretty obvious
> > that parallel transmission (read HT) is the way of the past. If you
> > look at any high performance interconnect, they are all serial. Talk
> > to the Rambus guys, they know what they are doing...
>
> Not quite, HT is a set of multiple serial interfaces. You can go from
> one to 16 unidirectional links, one to 16 in the other direction too.
> Exactly the same as PCI-e.

If I may quote from http://www.hypertransport.org/tech/tech_faqs.cfm:

"Serial technologies such as PCI Express and RapidIO require
serial-deserializer interfaces and have the burden of extensive
overhead in encoding parallel data into serial data, embedding clock
information, re-acquiring and decoding the data stream. The parallel
technology of HyperTransport needs no serdes and clock encoding
overhead making it far more efficient in data transfers."

Try to ignore the PR-speak in there, and focus on this part "The
parallel technology of HyperTransport".

HT is bit parallel and delivers at least 2 bits per cycle in parallel;
it's about as parallel as a PCI bus, it just happens to be much more
intelligently designed for the task at hand (and thankfully
unidirectional, and not multidrop).

Now, let me quote someone who knows quite a bit about CPU<->CPU
interconnects:

http://www.realworldtech.com/forums/index.cfm?action=detail&PostNum=3546&Thread=328&roomID=11&entryID=53843

"Using equivelent technology the bit serial scheme will have 2X+ the
datarate per pin. the latency differental is at worst 2 bit times but
can be exactly the same if not better depending on the actual protocol
being used."

PCIe is bit serial, HT, as I explained above, is not. Yes, the latency
is a little worse, but the amount of times it takes to transmit two
bits is pretty darn negligible for double the bandwidth.

David

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Tue, 26 Jul 2005 12:50:03 -0400, Yousuf Khan <bbbl67@ezrs.com>
wrote:

>Tony Hill wrote:
>> The slot is actually VERY similar to PCI-Express (same physical
>> connectors) and the specs are designed to make it easy to have both
>> PCI-E and HTX on the same board.
>
>I didn't realize that PCI-E and HTX had similar connectors. Is one an
>extension of the other (eg. HTX is a few extra slots beyond the PCIE
>slots, like VESA was compared to ISA), or something like EISA was to
>ISA, with somewhat deeper slots? Or are they totally incompatible but
>they look similar?

More like Slot 1 vs. Slot A. Same physical connector but turned
backwards (or at least that is my understanding of it). The
electrical specs are, not surprisingly, totally incompatible.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

"David Kanter" <dkanter@gmail.com> writes:

> Yousuf Khan wrote:
>> Del Cecchi wrote:
>> > HT can go maybe a foot, if you are really lucky. Work out the skew
>> > budgets. At 2000 MT, the board is allocated less than 100 ps as I recall.
>> >
>> > PCI-E on the other hand can go several meters.
>> >
>> > Totally different approaches.
>>
>> Which is why PCI-e never got adopted as a CPU to CPU interconnect.
>
> One never knows what the future holds. Anyway, it's pretty obvious
> that parallel transmission (read HT) is the way of the past. If you
> look at any high performance interconnect, they are all serial. Talk
> to the Rambus guys, they know what they are doing...

While a serial (and encoded) link is way easier to handle, the sky is
not the limit. Consider that at 10Gb/s standard FR-4 board material
have quite frightening losses, which limits the length you can send
it. The several meters that Del talk about is on cables, I think.

And just exactly why would you want to go several meters on a CPU to
CPU interconnect (at least in the x86 mass-market)?

Sure, the parallel link as other problems, also pointed out by Del,
but my point here is that blindly claiming that either technology is
the "right thing" is not a good idea.

Latency, bandwidth, die area, power consumption, and maximum trace
length should all be considered.

> Now, as to whether serial connections between CPUs is a good idea, I am
> not entirely sure; I suspect Del is far more qualified to discuss that
> topic than I am. Generally, serial connections can be driven far
> faster, but there is slighly longer latency for SERDES.

Definitely - and as we know: money can buy you bandwidth, but latency
is forever.

Think of the performace of SDRAMs - while the DDR's have awesome peak
BW numbers, they rarely translate into real-world benefits that is
worth taking about.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Kai Harrekilde-Petersen wrote:
> "David Kanter" <dkanter@gmail.com> writes:
>
>
>>Yousuf Khan wrote:
>>
>>>Del Cecchi wrote:
>>>
>>>>HT can go maybe a foot, if you are really lucky. Work out the skew
>>>>budgets. At 2000 MT, the board is allocated less than 100 ps as I recall.
>>>>
>>>>PCI-E on the other hand can go several meters.
>>>>
>>>>Totally different approaches.
>>>
>>>Which is why PCI-e never got adopted as a CPU to CPU interconnect.
>>
>>One never knows what the future holds. Anyway, it's pretty obvious
>>that parallel transmission (read HT) is the way of the past. If you
>>look at any high performance interconnect, they are all serial. Talk
>>to the Rambus guys, they know what they are doing...
>
>
> While a serial (and encoded) link is way easier to handle, the sky is
> not the limit. Consider that at 10Gb/s standard FR-4 board material
> have quite frightening losses, which limits the length you can send
> it. The several meters that Del talk about is on cables, I think.
>
> And just exactly why would you want to go several meters on a CPU to
> CPU interconnect (at least in the x86 mass-market)?
>
> Sure, the parallel link as other problems, also pointed out by Del,
> but my point here is that blindly claiming that either technology is
> the "right thing" is not a good idea.
>
> Latency, bandwidth, die area, power consumption, and maximum trace
> length should all be considered.
>
>
>>Now, as to whether serial connections between CPUs is a good idea, I am
>>not entirely sure; I suspect Del is far more qualified to discuss that
>>topic than I am. Generally, serial connections can be driven far
>>faster, but there is slighly longer latency for SERDES.
>
>
> Definitely - and as we know: money can buy you bandwidth, but latency
> is forever.
>
> Think of the performace of SDRAMs - while the DDR's have awesome peak
> BW numbers, they rarely translate into real-world benefits that is
> worth taking about.
>
>
> Kai
PCI express is an IO expansion network, I don't know where the cpu-cpu
talk came from. Architecturally it is sort of master slave.

As for length, it is limited by the loss budget to 8db of loss at
1.25GHz as I recall, and by ISI to about 100 ps. HT on the other hand
transmits data in parallel with a clock to provide timing and no
alignment so distance is limited primarily by skew as defined in the HT
spec.

The 2.5 Gbit interfaces like PCI-e can go a couple of feet on a
backplane. IB used 20 inches as an objective.

The serdes based standards do indeed have somewhat longer latency due to
the 10 bit penalty on each end. But HT also has to make the data wider
for convenient handling.

This kind of stuff is what I do. So I am familiar with the various
limitations.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

 

[mygarbage2000]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On 26 Jul 2005 11:05:21 -0700, "David Kanter" <dkanter@gmail.com>
wrote:
....snip previous msgs... - nnn
>One never knows what the future holds. Anyway, it's pretty obvious
>that parallel transmission (read HT) is the way of the past. If you
>look at any high performance interconnect, they are all serial. Talk
>to the Rambus guys, they know what they are doing...
Surely they know - they sue everyone and their mother in law (pun
intended)
nnn
>
>Now, as to whether serial connections between CPUs is a good idea, I am
>not entirely sure; I suspect Del is far more qualified to discuss that
>topic than I am. Generally, serial connections can be driven far
>faster, but there is slighly longer latency for SERDES.
>
>HT was never envisioned to replace PCI-X, PCI or anything else.
>Yousuf, you should at least try to distinguish yourself from AMD PR
>personnel...
>
>David