AMD's Future Chips & SoC's: News, Info & Rumours.

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So do you think we might see some kind of Zen core at TSMC? I mean if they don't have to pay global foundries extra its always nice to have a second supplier even more so when your main one is global foundries.
 


Well, depends on how GloFo wants to tune their node. It will also depend on TSMC's capacity I'd say.

Cheers!
 
Samsung Strengthens Advanced Foundry Portfolio with New 11nm LPP and 7nm LPP with EUV Technology
Korea on September 11, 2017


Samsung also confirms development of 7nm LPP
with EUV is on schedule

Samsung Electronics, the world leader in advanced semiconductor technology, today announced it has added 11-nanometer (nm) FinFET process technology (11LPP, Low Power Plus) to its advanced foundry process portfolio, offering customers with an even wider range of options for their next-generation products.

Through further scaling from the earlier 14LPP process, 11LPP delivers up to 15 percent higher performance and up to 10 percent chip area reduction with the same power consumption.

In addition to the 10nm FinFET process for mobile processors in premium flagship smartphones, the company expects its 11nm process to bring differentiated value to mid- to high-end smartphones.

The new process technology is scheduled to be ready for production in the first half of 2018.

Samsung also confirmed that development of 7LPP with EUV (extreme ultra violet) lithography technology is on schedule, targeting its initial production in the second half of 2018.

Since 2014, Samsung has processed close to 200,000 wafers with EUV lithography technology and, building on its experience, has recently seen visible results in process development such as achieving 80 percent yield for 256 megabit (Mb) SRAM (static random-access memory).

“Samsung has added the 11nm process to our roadmap to offer advanced options for various applications,” said Ryan Lee, Vice President and Head of Foundry Marketing at Samsung Electronics. “Through this, Samsung has completed a comprehensive process roadmap spanning from 14nm to 11nm, 10nm, 8nm, and 7nm in the next three years.”

Details of the recent update to Samsung’s foundry roadmap, including 11LPP availability and 7nm EUV development, will be elaborated at the Samsung Foundry Forum Japan on September 15, 2017, in Tokyo. The Samsung Foundry Forum was held in the United States and South Korea earlier this year, sharing Samsung’s cutting-edge process technologies with global customers and partners.

Nothing about AMD from the source.
 
Zen2 is 7nm.

TSMC 7nm and Glofo 7nm aren't compatible. AMD cannot use TSMC as "second source". I guess AMD will use TSMC for GPUs and Glofo for CPUs, because the Glofo process doesn't look suitable for GPUs.
 


Sounds like regular marketing speech. Nothing really relevant to take away, other than "we're not developing 7nm alone". I would imagine that 11nm node would be used primarily for things that can live with a less denser node and can tolerate higher power (or not in a efficiency driven market).

I would imagine AMD might take a look at their 7nm LPP for something (APUs? mobile chips?) and stick with GloFo for LP oriented stuff? Anyone seen any TSMC news as well?

Cheers!
 


TSMC has an event Wednesday, so we will learn more really soon. GlobalFoundries event is on the 30th, so 2 and a half weeks before we learn something.

Edit:
TSMC Open Innovation Platform (OIP) Forum
Visit Synopsys at the TSMC Open Innovation Platform (OIP) Forum


Synopsys has a long-standing collaboration with TSMC and a common commitment to provide designers with the best IP, tools, design flows and process technologies. Stop by the Synopsys booth (#716) to learn more about our design and IP solutions for the most advanced nodes.

Date: September 13, 2017
Hours: 8:30 a.m. to 6:35 p.m.
Location: Santa Clara Convention Center



Demo Stations

Learn about the following in the Synopsys Booth #716

IC Compiler II – The World Standard for High Performance P&R
Silicon-Proven FinFET Design Technology Leadership
Custom Design and AMS Verification for FinFETs
Silicon-Proven IP for FinFET Processes

See the new Bluetooth solution:

Complete Bluetooth Low Energy Link Layer and PHY IP

This demonstration features Synopsys’ complete DesignWare® Bluetooth Low Energy IP solution operating in two distinct roles – as a central device and a peripheral device. Synopsys’ Bluetooth Low Energy IP solution is compliant with Bluetooth 5 and Bluetooth mesh, and offers a compact, low-power wireless IP solution for IoT applications like wearables, smart home and smart city/industrial.



Synopsys at TSMC OIP Ecosystem Forum 2017

EDA Track:

Improving Physical Verification Performance and Productivity for Latest GPU Designs [Joint paper with Nvidia]

Maximizing ROI for 7nm SoCs with Synopsys’ Convergent Digital Design Platform

HiSilicon Achieves PPA Targets Quicker Using PrimeTime POCV to Reduce Design Margin on TSMC N7 FinFET process [Joint paper with HiSilicon]

Stacked Device Enablement for Advanced Analog Design Simulations [Joint paper with Xilinx]

IP Track:

Foundation IP for High-Performance Computing Designs on TSMC N7 FinFET Process

Accelerating Development of Automotive ADAS SoCs with Certified IP
 
Synopsys Successfully Tapes Out Broad IP Portfolio for TSMC 7-nm FinFET Process
DesignWare Foundation and Interface IP on TSMC 7-nm Process Technology Enables Faster Time-to-Market for Mobile, Automotive and High-Performance Computing SoCs

MOUNTAIN VIEW, Calif. -- Sept. 11, 2017 -- Synopsys, Inc. (Nasdaq: SNPS) today announced the successful tape-out of a broad portfolio of DesignWare® Foundation and Interface PHY IP for TSMC's 7-nm process technology, including logic libraries, embedded memories, embedded test and repair, USB 3.1/2.0, USB-C 3.1/DisplayPort 1.4, DDR4/3, MIPI D-PHY, PCI Express® 4.0/3.1, Ethernet and SATA 6G. Additional DesignWare IP, including LPDDR4x, HBM2 and MIPI M-PHY, is scheduled to tape out in 2017. TSMC's 7-nm process enables designers to achieve up to a 60 percent power reduction or 35 percent performance increase compared to the 16FF+ process. By providing a portfolio of IP on TSMC's latest 7-nm process technology, Synopsys enables designers to meet the power and performance requirements of their mobile, automotive and high-performance computing applications.

"For more than a decade, Synopsys and TSMC have collaborated closely to provide high-quality IP for many generations of TSMC's processes," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Synopsys' tape-out of a broad portfolio of DesignWare Foundation and Interface IP for TSMC's 7-nm process demonstrates its ongoing leadership in providing IP that enables our mutual customers to take advantage of the power, performance and area improvements offered by the process, while accelerating designers' time to volume production."

"As the leading provider of physical IP with more than 100 FinFET tape-outs, Synopsys makes significant investments in developing IP for the most advanced processes so that our customers can implement the necessary functionality to differentiate their SoCs," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "The successful tape-out of a broad range of DesignWare Foundation and Interface IP on TSMC's 7-nm technology gives designers confidence that they can integrate our IP into their SoC with significantly less risk and accelerate their project schedule."

Availability

A portfolio of DesignWare Foundation and Interface IP for the TSMC 7-nm process is available now. The STAR Memory System™ solution is also available now for all TSMC process technologies.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
 
Thanks for that.

Too much marketing speak; nothing really relevant to take away, other than it looks like nVidia is well embedded in their line up. They do mention "automotive" as it's own thing, so that smell like nVidia alright. Everything else seems generic for any company.

Cheers!
 


TSMC's 7-nm process enables designers to achieve up to a 60 percent power reduction or 35 percent performance increase compared to the 16FF+ process.


Vega needs 7nm, the damn thing consumes too much power. Also, there is strong push to eliminate PCI-E power connectors.

Hot Chips 2017: We'll See PCIe 4.0 This Year, PCIe 5.0 In 2019
by Paul Alcorn August 29, 2017 at 6:30 AM

aHR0cDovL21lZGlhLmJlc3RvZm1pY3JvLmNvbS9DLzEvNzA2NzUzL29yaWdpbmFsLzEwMC5QTkc=

Link the post I made in Vega Mega Thread

Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
 
AMD finally agrees to pay to investors that denounced that AMD made "false and misleading statements to investors about the manufacturing and subsequent launch of, as well as the demand for, its Llano microprocessor"

https://www.theregister.co.uk/2017/08/28/amd_drops_295m_on_llano/

I guess AdoredTV will not make any video about this.
 


This is precisely the truth of it. AMD's agreement with GloFo only invokes a penalty if the purchase of wafers falls below a minimum threshold. What AMD does beyond that is no concern of GloFo.
 


Did you know Intel is about to lose their decade long fight with EU courts over their billion dollar fine?
 


The supreme EU cort just settled the appeal in Intel favor.
 


That AM4 upgrade path is not confirmed. The only confirmed AM4 socket processor is Pinnacle Ridge. And even if it is finally confirmed that AM4 will last until 2020, AM4 customers will miss updates as DDR5 and PCIe4.
 


Scroll up
Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
 

Yeah it's still far to early for DDR5 and PCI-E 4.0 to become mainstream anyways. They can't even get DDR4 ram prices in check last thing they should be worrying about is a newer standard.

AM4 will probably be around until 2020 and with Zen3. PCI-E 4.0 isn't even needed with a 1080Ti.
 


PCi4 SSDs are scheduled for next year.
 


Most likely we will see AM4 be like AM3 meaning new chipsets will come out for Zen 2 and 3 but they will work on older chipsets too depending on bios updates. For PCI-E 4.0 it will probably just be in a newer chipset and it will provide 1-3% difference for 3 years at least for games.

But i will say not a lot of people need a new board when upgrading but the platform forces the user too. On forums every day i hear people wanting to upgrade their 2500K(or worse i3-3220) to something modern be nice to put a haswell chip in it or better since the board still has USB 3.0, PCI-E 3.0 basically all most in this community cares to have.

Taking a look at the ASUS P8Z77-V LK it still has 4 USB 3.0 connections, 2 PCI-E 3.0 X16 slots, basically all its missing is a M.2 slot which basically doesn't offer major noticeable differences compared to a SATA SSD for most people who just game.

Still waiting on Intel to explain in full detail why users have to upgrade their 2016-2017 Z170, Z270 boards which have adequate VRM for a 6 core coffee-lake CPU when it has the exact pin layout.

I would understand them locking it out on weaker boards do to VRM quality but not everyone. In todays world with the north bridge and south bridge being integrated into the CPU it just doesn't make a lot of sense to have to upgrade their boards everytime a new CPU comes out.

I'll be happy to put a Zen 3 based CPU in my ASRock X370 Taichi in 2020 and not have to spend 200$ more on a board when mine still has all the connections i need and want.
 


AMD seems to be doing as much as they can to come back in a big way. I am using the Model P8Z77-V with my i5 2500K. It's still a great board and processor. I decided to wait to see what the next node shrink offers before I make my decision to upgrade. I've had my eye on AMD since GlobalFoundries and IBM teamed up, and started making working 7, and 5nm chips. 8 real cores for under $300 is just amazing. And the upgrade path on AM4 till 2020! It's ideal and so much cheaper than Intel has ever been! We will find out more about the semiconductor situation with GlobalFoundries next Wednesday! Let's hope they make their first product on time lol!
 


Do you have a creditable source as a point of reference?

 
anyone know about Pinnacle Ridge? i'm saving dollars for a build next year and it looks like it'll be pinnacle ridge if it's available 2018. hope its a slightly speed bumped ryzen 😀
 


I haven't been able to find any information on it. Hopefully next week on the 20th we might find out more about where GlobalFoundries is in it's development of 7nm.

2017 GlobalFoundries Technical Conference
When: September 20th 2017
Where: Hyatt Regency Santa Clara

At the GLOBALFOUNDRIES Technical Conference (GTC) in Santa Clara, learn how GF is collaborating with customers and industry leaders to deliver technologies enabling connected intelligence.

Our morning General Session is highlighted by a keynote from guest speaker Cristiano Amon, Executive Vice President, Qualcomm Technologies, Inc. and President, Qualcomm CDMA Technologies.

The General Session also features presentations from GF executives representing key areas of our business. Speakers will discuss market directions and what's new from GF, including the latest developments in process technology, design enablement, IP and RF, and include:
Sanjay Jha, CEO
Dr. Gary Patton, CTO and SVP, Worldwide R&D
Alain Mutricy, SVP, Product Management Group
Dr. Bami Bastani, SVP, RF Business Unit
Michael Cadigan, SVP, Global Sales and Business Development
The afternoon session showcases Technology and Solutions tracks that enable you to choose from a broad range of topics, including:
FDX™ design and ecosystem
IoT, 5G/networking and automotive solutions
Intelligent applications
FDX, FinFET and RF technologies
Embedded memory solutions and mainstream platforms
GF ecosystem partners will be exhibiting in our Exhibition Hall, giving you the opportunity to explore how they can help you develop differentiated solutions:
 
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