goldstone77
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AMD renegotiated the deal, and already paid out the money! We don't know the specifics of the deal, and since money has already been paid there is obviously a plan in place!
Samsung Electronics, the world leader in advanced semiconductor technology, today announced it has added 11-nanometer (nm) FinFET process technology (11LPP, Low Power Plus) to its advanced foundry process portfolio, offering customers with an even wider range of options for their next-generation products.
Through further scaling from the earlier 14LPP process, 11LPP delivers up to 15 percent higher performance and up to 10 percent chip area reduction with the same power consumption.
In addition to the 10nm FinFET process for mobile processors in premium flagship smartphones, the company expects its 11nm process to bring differentiated value to mid- to high-end smartphones.
The new process technology is scheduled to be ready for production in the first half of 2018.
Samsung also confirmed that development of 7LPP with EUV (extreme ultra violet) lithography technology is on schedule, targeting its initial production in the second half of 2018.
Since 2014, Samsung has processed close to 200,000 wafers with EUV lithography technology and, building on its experience, has recently seen visible results in process development such as achieving 80 percent yield for 256 megabit (Mb) SRAM (static random-access memory).
“Samsung has added the 11nm process to our roadmap to offer advanced options for various applications,” said Ryan Lee, Vice President and Head of Foundry Marketing at Samsung Electronics. “Through this, Samsung has completed a comprehensive process roadmap spanning from 14nm to 11nm, 10nm, 8nm, and 7nm in the next three years.”
Details of the recent update to Samsung’s foundry roadmap, including 11LPP availability and 7nm EUV development, will be elaborated at the Samsung Foundry Forum Japan on September 15, 2017, in Tokyo. The Samsung Foundry Forum was held in the United States and South Korea earlier this year, sharing Samsung’s cutting-edge process technologies with global customers and partners.
Samsung Electronics, the world leader in advanced semiconductor technology, today announced it has added 11-nanometer (nm) FinFET process technology (11LPP, Low Power Plus) to its advanced foundry process portfolio, offering customers with an even wider range of options for their next-generation products.
Through further scaling from the earlier 14LPP process, 11LPP delivers up to 15 percent higher performance and up to 10 percent chip area reduction with the same power consumption.
In addition to the 10nm FinFET process for mobile processors in premium flagship smartphones, the company expects its 11nm process to bring differentiated value to mid- to high-end smartphones.
The new process technology is scheduled to be ready for production in the first half of 2018.
Samsung also confirmed that development of 7LPP with EUV (extreme ultra violet) lithography technology is on schedule, targeting its initial production in the second half of 2018.
Since 2014, Samsung has processed close to 200,000 wafers with EUV lithography technology and, building on its experience, has recently seen visible results in process development such as achieving 80 percent yield for 256 megabit (Mb) SRAM (static random-access memory).
“Samsung has added the 11nm process to our roadmap to offer advanced options for various applications,” said Ryan Lee, Vice President and Head of Foundry Marketing at Samsung Electronics. “Through this, Samsung has completed a comprehensive process roadmap spanning from 14nm to 11nm, 10nm, 8nm, and 7nm in the next three years.”
Details of the recent update to Samsung’s foundry roadmap, including 11LPP availability and 7nm EUV development, will be elaborated at the Samsung Foundry Forum Japan on September 15, 2017, in Tokyo. The Samsung Foundry Forum was held in the United States and South Korea earlier this year, sharing Samsung’s cutting-edge process technologies with global customers and partners.
Samsung Electronics, the world leader in advanced semiconductor technology, today announced it has added 11-nanometer (nm) FinFET process technology (11LPP, Low Power Plus) to its advanced foundry process portfolio, offering customers with an even wider range of options for their next-generation products.
Through further scaling from the earlier 14LPP process, 11LPP delivers up to 15 percent higher performance and up to 10 percent chip area reduction with the same power consumption.
In addition to the 10nm FinFET process for mobile processors in premium flagship smartphones, the company expects its 11nm process to bring differentiated value to mid- to high-end smartphones.
The new process technology is scheduled to be ready for production in the first half of 2018.
Samsung also confirmed that development of 7LPP with EUV (extreme ultra violet) lithography technology is on schedule, targeting its initial production in the second half of 2018.
Since 2014, Samsung has processed close to 200,000 wafers with EUV lithography technology and, building on its experience, has recently seen visible results in process development such as achieving 80 percent yield for 256 megabit (Mb) SRAM (static random-access memory).
“Samsung has added the 11nm process to our roadmap to offer advanced options for various applications,” said Ryan Lee, Vice President and Head of Foundry Marketing at Samsung Electronics. “Through this, Samsung has completed a comprehensive process roadmap spanning from 14nm to 11nm, 10nm, 8nm, and 7nm in the next three years.”
Details of the recent update to Samsung’s foundry roadmap, including 11LPP availability and 7nm EUV development, will be elaborated at the Samsung Foundry Forum Japan on September 15, 2017, in Tokyo. The Samsung Foundry Forum was held in the United States and South Korea earlier this year, sharing Samsung’s cutting-edge process technologies with global customers and partners.
DesignWare Foundation and Interface IP on TSMC 7-nm Process Technology Enables Faster Time-to-Market for Mobile, Automotive and High-Performance Computing SoCs
MOUNTAIN VIEW, Calif. -- Sept. 11, 2017 -- Synopsys, Inc. (Nasdaq: SNPS) today announced the successful tape-out of a broad portfolio of DesignWare® Foundation and Interface PHY IP for TSMC's 7-nm process technology, including logic libraries, embedded memories, embedded test and repair, USB 3.1/2.0, USB-C 3.1/DisplayPort 1.4, DDR4/3, MIPI D-PHY, PCI Express® 4.0/3.1, Ethernet and SATA 6G. Additional DesignWare IP, including LPDDR4x, HBM2 and MIPI M-PHY, is scheduled to tape out in 2017. TSMC's 7-nm process enables designers to achieve up to a 60 percent power reduction or 35 percent performance increase compared to the 16FF+ process. By providing a portfolio of IP on TSMC's latest 7-nm process technology, Synopsys enables designers to meet the power and performance requirements of their mobile, automotive and high-performance computing applications.
"For more than a decade, Synopsys and TSMC have collaborated closely to provide high-quality IP for many generations of TSMC's processes," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Synopsys' tape-out of a broad portfolio of DesignWare Foundation and Interface IP for TSMC's 7-nm process demonstrates its ongoing leadership in providing IP that enables our mutual customers to take advantage of the power, performance and area improvements offered by the process, while accelerating designers' time to volume production."
"As the leading provider of physical IP with more than 100 FinFET tape-outs, Synopsys makes significant investments in developing IP for the most advanced processes so that our customers can implement the necessary functionality to differentiate their SoCs," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "The successful tape-out of a broad range of DesignWare Foundation and Interface IP on TSMC's 7-nm technology gives designers confidence that they can integrate our IP into their SoC with significantly less risk and accelerate their project schedule."
Availability
A portfolio of DesignWare Foundation and Interface IP for the TSMC 7-nm process is available now. The STAR Memory System™ solution is also available now for all TSMC process technologies.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
TSMC's 7-nm process enables designers to achieve up to a 60 percent power reduction or 35 percent performance increase compared to the 16FF+ process.
Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
AMD plans to support its Socket AM4 for all of its processors until 2020, so Intel’s lack of backward compatibility with existing 200-series chipsets will likely dominate the conversation.
AMD plans to support its Socket AM4 for all of its processors until 2020, so Intel’s lack of backward compatibility with existing 200-series chipsets will likely dominate the conversation.
AMD plans to support its Socket AM4 for all of its processors until 2020, so Intel’s lack of backward compatibility with existing 200-series chipsets will likely dominate the conversation.
Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
AMD plans to support its Socket AM4 for all of its processors until 2020, so Intel’s lack of backward compatibility with existing 200-series chipsets will likely dominate the conversation.
Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
AMD plans to support its Socket AM4 for all of its processors until 2020, so Intel’s lack of backward compatibility with existing 200-series chipsets will likely dominate the conversation.
Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
AMD plans to support its Socket AM4 for all of its processors until 2020, so Intel’s lack of backward compatibility with existing 200-series chipsets will likely dominate the conversation.
Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
AMD plans to support its Socket AM4 for all of its processors until 2020, so Intel’s lack of backward compatibility with existing 200-series chipsets will likely dominate the conversation.
Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
AMD plans to support its Socket AM4 for all of its processors until 2020, so Intel’s lack of backward compatibility with existing 200-series chipsets will likely dominate the conversation.
Intel and AMD are the key enablers for the broad desktop market; we certainly won't see PCIe 4.0 GPUs and SSDs without a slot to plug them into. AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
At the GLOBALFOUNDRIES Technical Conference (GTC) in Santa Clara, learn how GF is collaborating with customers and industry leaders to deliver technologies enabling connected intelligence.
Our morning General Session is highlighted by a keynote from guest speaker Cristiano Amon, Executive Vice President, Qualcomm Technologies, Inc. and President, Qualcomm CDMA Technologies.
The General Session also features presentations from GF executives representing key areas of our business. Speakers will discuss market directions and what's new from GF, including the latest developments in process technology, design enablement, IP and RF, and include:
Sanjay Jha, CEO
Dr. Gary Patton, CTO and SVP, Worldwide R&D
Alain Mutricy, SVP, Product Management Group
Dr. Bami Bastani, SVP, RF Business Unit
Michael Cadigan, SVP, Global Sales and Business Development
The afternoon session showcases Technology and Solutions tracks that enable you to choose from a broad range of topics, including:
FDX™ design and ecosystem
IoT, 5G/networking and automotive solutions
Intelligent applications
FDX, FinFET and RF technologies
Embedded memory solutions and mainstream platforms
GF ecosystem partners will be exhibiting in our Exhibition Hall, giving you the opportunity to explore how they can help you develop differentiated solutions: