AMD's Future Chips & SoC's: News, Info & Rumours.

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It's quite possible to wrap the legacy x86 instructions around x64 counterparts.

*shrug*
 


That might be so, but there's a penalty to do that. Unless AMD designed Zen, from scratch, with that in mind. That would be really cool, but I really have to wonder what the penalty of that would be on the front decoders.

So, this is to say, I hardly believe they gave only "X86-64 Zen" to them.

Cheers!
 


The penalty wouldn't be too bad; remember your dealing with complex instructions most of the time anyway. Instead of reducing "Z" to "X" and "Y", you reduce to "A" and "B". Provided you have 1:1 replacements, most of this process should be free.

That being said, until we know more, we're just going off speculation.
 
I actually don't like that. AMD is just being a <insert phallic word here> on Intel's celebration. You don't go to other people's weddings to announce your own marriage, right? There are some lines they should not cross IMO and this is one of them.

Now, I can't deny Intel deserves it, but I still find it of bad taste.

Cheers!
 

goldstone77

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Also, notice it says ThreadRipper on the Ryzen graphic as well.
 

jaymc

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(Rumor) Zen 2 Design Leak
Just saw this on FB posted by Lukasz Lis who seems to be an insider and provide the group with pretty solid news.

"The ZEN2 DESIGN INDUSTRY LEAK

I just received a some "Take it with sea of salt" Industry leaks about Zen2 architecture design.

Zen2 will shift from 4 core per CCX to 6 core per CCX in mainstream.

there will be 2 die designs. Mainstream using 2x 6 core CCX, giving up to 12 cores per one die. And High performance die, using a 16 core native design, where I could not get anything about CCX design. In theory it will be server-based multithreading demon, build on 4x 4core-cx design (EPYC multi-die design in one die) or 2x 8 core in CCX. Loads of salt.

Due massive 7nm node improvements in both thermals and voltage requirement, all zen2 chips should come 4ghz stock.

AMD may improve floating point performance of Zen2 by changing 128-bit FMUL/FADDs to a 256bit FMAC (Multiply–accumulate operation)

Remember. This is just a rumors. Some of them covers with other websites, some of them may show up at some point or not. However. While it sound reasonable, I would say take it with a massive shovel of salt. Zen2 design can be both big success or massive failure of AMD."
 

jaymc

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Hey Guy's, Iooks like the rumour mill is in full swing.

I got that one on the AMD stock subreddit, it came from FB orginally apparantly.... (please grab your salt sellers) but howenever.
https://www.reddit.com/r/AMD_Stock/comments/8sblxy/rumor_zen_2_design_leak/

Well if Zen 2 is made from 8 core CCX's then it's possible the 6 core CCX's are actually 8 core CCX's with two dud / fused off or just not up to scratch cores i.e lower binned / failed 8 core CCX's...
Yield rates may not be as high if they move to an 8 core CCX.. an it would make sense to bin the failed 8 core CCX's as 6 etc CCX's I guess.

This all fits nicely into a 64 core, 128 thread Epyc 2 CPU.

Kinda sounds like a fairly reasonable (albeit obvious) deduction.

But what do yis make of the 4ghz base clock, hopefully we get a little more than that. But lets just assume the core count doubles in Desktop and HDET... I would still be hoping to see a little more than that. 400 or 500mhz increase would be nice, or is that just asking for too much ?

Maybe I'm just being greedy... still though.. :D
 

goldstone77

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AMD’S EPYC RETURN TO THE DATACENTER RING
June 20, 2018 Timothy Prickett Morgan

McCarron says that AMD’s share of the server space hit rock bottom at the beginning of 2017, with a mere 0.3 percent of shipments based on the prior Opterons. McCarron says that in the wake of the Epyc launch, AMD was able to garner around 1 percent share in the first quarter of 2018, and even though the second quarter still not done, he is forecasting that Epyc volumes are on a power of 2 ramp and will double every quarter for a while. AMD has been very clear that it hopes to exit 2018 with 5 percent shipment share and then build to a respectable double-digit share – that can be anywhere from 10 percent to 99 percent, of course – in the years after that. McCarron says that 5 percent by the end of 2018 is absolutely doable.

Our plan for the Naples-Rome-Milan roadmap was based on assumptions around Intel’s roadmap and our estimation of what would we do if we were Intel,” Norrod continues. “We thought deeply about what they are like, what they are not like, what their culture is and what their likely reactions are, and we planned against a very aggressive Intel roadmap, and I really Rome and Milan and what is after them against what we thought Intel could do. And then, we come to find out that they can’t do what we thought they might be able to. And so, we have an incredible opportunity. Rome was designed to compete favorably with “Ice Lake” Xeons, but it is not going to be competing against that chip. We are incredibly excited, and it is all coming together at one point. We have reintroduced ourselves to the market, gotten the initial traction and wins, we got the initial customer support, and we validated that AMD is a safe choice with an effective processor. With the Rome processor and process, we are going to be in an incredible position going forward.”
https://www.nextplatform.com/2018/06/20/amds-epyc-return-to-the-datacenter-ring/
 

jaymc

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Excellent Read... Very exciting stuff !

It's been a wild ride an it looks like the battle for the server market is only really starting to hot up..

Just as AMD threatens to give Intel the old one-two. Everything seem's to be falling into place for AMD at long last and Intel's luck seem's to be running out as 10nm is delayed even still and Intel's CEO is forced to step down. It's better than any soap opera at the moment. Things appear to be unfolding so far anyway, just as so many people have said they would it almost seem's inevitable at this point in time dare I say the words but "A tectonic shift is taking place in the IT Industry"
 

jdwii

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Man i miss the old days here where we had several pages of material to read now i feel like this place got a bit boring.


Anyways i love that Amd and Intel have been trolling each other lately. Maybe Intel will pull something out of a hat but really i don't see X86 going much further i mean its 2018 and we really haven't seen much.
 

goldstone77

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Before 2017, how much did you see before? There is at least 2 companies putting out compelling products now. AMD has ThreadRipper Heavy Metal edition coming out 24 and 32 cores. Intel has Coffee Lake refresh, which is going to have an 8 core CPU. We will have to wait till the end of the year to find out details on 7nm performance for next year.
 

jdwii

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Basically what i feared seems to be true focusing on moar cores over per core performance i guess it will bite them in the end when Intel simply raises core counts
 

goldstone77

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I think it's just people making stuff up. Lisa Su said she would share specs at the end of the year. ~5 months and counting! We know that Rome is going to be 48 cores, and it's thought that Milan is going to be 64 cores. TSMC 7nm HPC is 4.4GHz targeting high performance and mobile. And GloFo has not finished tapping out 7nm. We know TSMC is making 7nm Vega and Rome for AMD. Launching 2H2018, and 1H2019 respectively. Now, we have some uncertainties, Desktop and APU. We know TSMC and GoFlo are supposed to both produces chips for AMD, but Lisa Su was not totally clear how this was going to be dived up.
 

jaymc

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That's a very good point. We are still trailing with IPC at the mo.. granted the shrink should put us ahead. Well I'm sure they will still be selling 8 cores right.. surely their will be plenty of head room there per per watt after the shrink ? It seem's AMD's hole advantage is in parallel compute "at the moment anyway " and the scaling quality of IF.

How much do we really know about this EMIB, I know that the "MESH" causes a hit when compared to the "RING" system for core to core communication.

How much of a clock speed bump are we looking at, obviously it depends on core count but lets say on an 8 core Ryzen, if they get it running at 4.4ghz as Goldstone77 say's their node is targeting, how much of an IPC gain does that translate to, without any changes in architecture or low hanging fruit for that matter ?
 

jaymc

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Hey Goldstone77, yeah you probably right mate looks could be just guesses alright.

Is that 4.4ghz target from their node a base clock speed ?

If so that pretty beastly I mean that would be a 700mhz improvement over the 2700x that would be amazing...
Also I guess the if they are going to 48 cores in Epyc 2 that leaves more head room for perf per watt / clock increase.
 

jaymc

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Check this out it's a right riveting read ;-)

Looking at recent AMD patents: Chiplets, scalable designs, Navi and how AMD plans to dominate from mobile/ultraportable to HPC/AI to Datacenter.
https://www.reddit.com/r/AMD_Stock/comments/8tl31y/looking_at_recent_amd_patents_chiplets_scalable/
 

goldstone77

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I'm not sure how much overclocking room would be tied to the 4.4GHz for the 7nm HPC, all I know is that it was what they claim for 7nm HPC.
 

goldstone77

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Wow, and interesting!
Here they describe a very low power coprocessor for a cpu that is consisted of a single sSIMD unit (remember this is only a subcomponent of a gpu as we know it). This is a truly heterogenous design, in the example they give a SIMD unit can assist the cpu with scheduling tasks that cannot be parallelized (network package processing, cryptography, audio etc).

What this means is that when, because of the nature of the task in a software, multiple cores cannot be used, you can use the coprocessor to increase single core performance with minimal power cost! Note that on the same cpu there may be also a full igpu as we know it as well as the coprocessor, so the coprocessor is not a gpu by a different name, it is a subcomponent of the cpu that was built for purpose using parts of a gpu.

And it doesn't even have to be a x86 cpu, it can be used with literally any kind of processor.
 

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