Yes, I have a lot of respect for Hans. He was the one who refuted the notion that K8L had 4 instruction issue. It is too bad that he stopped posting technical articles on his website. Those were first rate. I know of another gentleman who did very detailed analysis of memory and cache on AMD and Intel processors but then he stopped when K8 was introduced.
That thread you linked to was brutal. It had already deteriorated into flaming by the 2nd page and just got worse from there. Yes, it does have real information in it but the flames and personal attacks really knock things down. I once described that on AMDZ as like eating ice cream with sawdust in it. This thread is going smoothly with lots of information and discussion and no flames and that makes a huge difference in how easy it is to read.
Yes, everything I've seen would suggest 64KB's each for Data and Instructions. BTW, I've just seen at AMD their latest press release is Ultimate Datacenter Performance-Per-Watt. This again makes me think that the 40% number is mostly power draw and not processor speed.
Later version CPUs will have DDR-3 support, but for Barcelona and its derivatives, they only integrate two 64-bit DDR-2 memory controllers.![]()
Later version CPUs will have DDR-3 support, but for Barcelona and its derivatives, they only integrate two 64-bit DDR-2 memory controllers.![]()
Later version CPUs will have DDR-3 support, but for Barcelona and its derivatives, they only integrate two 64-bit DDR-2 memory controllers.![]()
The sAM2+ and s1207+(Quad FX) will support 1067MHz unbuffered DRAM:
2channels x 64bit x 1066.666MHz = 136Gb/s = 17GB/s or 8.5GB/s per channel
The s1207(Opteron 2xxx/8xxx) will support 667MHz buffered DRAM:
2channels x 64bit x 666.666MHz = 85.3Gb/s = 10.7GB/s or 5.3GB/s per channel
The sAM2+ and s1207+(Quad FX) will support 1067MHz unbuffered DRAM:
2channels x 64bit x 1066.666MHz = 136Gb/s = 17GB/s or 8.5GB/s per channel
The s1207(Opteron 2xxx/8xxx) will support 667MHz buffered DRAM:
2channels x 64bit x 666.666MHz = 85.3Gb/s = 10.7GB/s or 5.3GB/s per channel
Oh..I thought that he was speaking about bandwidth. It would be the same as for the K8. The s1207 with buffered ODMC will support 4GB per channel, while the unbuffered ODMC will support 2GB per channel.
My thinking was along the lines of this. AMD will probably match the power draw of C2D. However, a dual or quad FSB northbridge would draw more power and FBDIMM would draw more still. They would need 29% less power draw in a system comparison to hit the 40% number. It is difficult to say because they could also be doing Tulsa comparisons since this is currently the only 4-way. I'm certain they will have plenty of slides on this by the June Analysts Meeting. The big question is if they will have anything sooner. Supposedly, there will be limited deliveries of Barcelona in Q2 however, actual volume looks like Q3.Yeah, I noticed that verbage in other articles --- 40% Pref/watt sound more reasonable that a straight up 40% per clock IPC advantage.
We had the same discussion on AMDZ and concluded that the cache size eliminated ZRAM and there was also a lot of doubt that ZRAM would be fast enough. I had still been wondering though if TTRAM would be fast enough and it too is small than SRAM. Lately I've been wondering if AMD has any ideas about using ZRAM for video buffering with an on-die GPU.Parrot challenged the notion of ZRAM in the L3 cache which created some decent snooping around to figure out that, at least in this die shot, ZRAM is not operative.
OK, let's see if I got this straight:
The sAM2+, 1067MHz unbuffered DRAM:
4GB Total RAM in single CPU config.
The s1207+(Quad FX), 1067MHz unbuffered DRAM:
8GB Total RAM in dual CPU config.
The s1207(Opteron 2xxx/8xxx) will support 667MHz buffered DRAM:
8GB Total RAM in single CPU config. 16GB Total RAM in dual CPU config.
Right? :?
Not sure what you mean. The P4 line will end with Tulsa. C2D is derived from PIII. PIII->Banias/Dothan->Yonah->C2D. However, C2D will continue to evolve every two years according to Intel and AMD will also change the architecture.as the core2duo is the last iteration of the p6 line, barcelona will be the last for the k7
No. The only area where AMD might still have a big lead is in purely stack based FP computations. I don't see a big lead by either company in SSE or Integer.......surely that the perfs will be significantly higher than its intel s coutepart
An actual improvement in IPC of 42% would be nearly impossible. AMD gained about 20% with K8 over K7. Intel gained about 20% with Pentium M over PIII and about same with C2D. AMD will need another jump of about 20% to match C2D....amd claim some 42 % improvement in certain tasks..more realistically, it will be closer to a solid 20%, according to ipc improvement available...
No. You are wrong. AMD's hardware doubling on SSE plus doubling of the L1 cache bus and instruction Prefetch will match what Intel already has. Intel had the same doubling from Yonah to Conroe. That is why Conroe is much faster in SSE.the main advantage of the core duo is its 128 bit sse units, while amd s k8 only offer 64 bit see unit...with a width of 128 bit execution unit, along with the 4 instructions/cycle capability, this processor will blow up intel s product
AMD is making an even bigger push to reduce the time to 45nm; are they desperate too? You need to understand that quad cores are big chips and are much more economical on 45nm than 65nm for both Intel and AMD...that s why intel is desesperatly pushing for 45 nm,
OK, let's see if I got this straight:
The sAM2+, 1067MHz unbuffered DRAM:
4GB Total RAM in single CPU config.
The s1207+(Quad FX), 1067MHz unbuffered DRAM:
8GB Total RAM in dual CPU config.
The s1207(Opteron 2xxx/8xxx) will support 667MHz buffered DRAM:
8GB Total RAM in single CPU config. 16GB Total RAM in dual CPU config.
Right? :?
See the updated one![]()
See the updated one![]()
They currently support 4 sticks per channel with registered memory and 2 sticks per channel with unregistered. Since 2GB is the common memory size this would be:And I have also found out that from AMD's technical paper,
the maximum support memory is 16GB for one Socket F CPU 8O
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
Page 98
Updated: from page 32 of the same document, the maximum memory supported for Socket AM2 will be 8GB, the same as claimed by Asus.
They currently support 4 sticks per channel with registered memory and 2 sticks per channel with unregistered. Since 2GB is the common memory size this would be:
unregistered - 2 channels X 2 sticks X 2GB = 8GB total
registered - 2 channels X 4 sticks X 2GB = 16GB total
The memory controller itself can handle up to 16GB per DIMM. So, if 4GB DDR2 DIMMs are released soon anything from Revision F and up can handle it. The maximum speed for Revision F and G is DDR2-800 so Barcelona does support a bit faster speed with DDR2-1066.
They currently support 4 sticks per channel with registered memory and 2 sticks per channel with unregistered. Since 2GB is the common memory size this would be:And I have also found out that from AMD's technical paper,
the maximum support memory is 16GB for one Socket F CPU 8O
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
Page 98
Updated: from page 32 of the same document, the maximum memory supported for Socket AM2 will be 8GB, the same as claimed by Asus.