Hyper Transport?

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HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency computer bus that was introduced on April 2, 2001. The HyperTransport Technology Consortium is in charge of promoting and developing HyperTransport technology. The technology is used by AMD and Transmeta in x86 processors, PMC-Sierra, Broadcom, and Raza Microelectronics in MIPS microprocessors, ATI Technologies, NVIDIA, VIA, SiS, ULi/ALi, AMD, Apple Computer and HP in PC chipsets, HP, Sun Microsystems, IBM, and IWill in servers, Cray, Newisys, and PathScale in high performance computing, and Cisco Systems in routers. Notably missing from this list is semiconductor giant Intel, which continues to use a shared bus architecture.
HyperTransport comes in three versions — 1.0, 2.0, and 3.0 — which run from 200MHz to 2.6GHz (compared to PCI at either 33 or 66 MHz). It is also a DDR or "Double Data Rate" connection, meaning it sends data on both the rising and falling edges of the clock signal. This allows for a maximum data rate of 5200 MTransfers/s when running at 2.6GHz; this frequency is auto-negotiated.

HyperTransport supports an auto-negotiated bit width, based on two 2-bit lines to 32-bit lines. The full-sized, full-speed, 32-bit interconnect in each direction has a transfer rate of 20,800 MByte/s (5200 MT/s * (32 bits / 8)), making it much faster than many existing standards. Buses of various widths can be mixed together into a single application (for example, 2x8 instead of 1x16), which allows for higher speed interconnects between main memory and the CPU, and lower speed interconnects among peripherals as appropriate. The technology also has much lower latency than other solutions.

HyperTransport is packet-based, with each packet always consisting of a set of 32-bit words, regardless of the physical width of the connection. The first word in a packet is always a command word. If a packet contains an address, then the last 8 bits of the command word are chained with the next 32-bit word in order to make a 40-bit address. An additional 32-bit control packet is allowed to be prepended when 64-bit addressing is required. The remaining 32-bit words in a packet are the data payload. Transfers are always padded to a multiple of 32 bits, regardless of their actual length.

HyperTransport packets enter the interconnect in segments known as bit times. The number of bit times that it necessitates depends on the width of the interconnect. HyperTransport can be used for generating system management messages, signaling interrupts, issuing probes to adjacent devices or processors, and general I/O and data transactions. There are usually two different kinds of write commands that can be used - posted and non-posted. Posted writes are ones that do not require a response from the target. This is usually used for high bandwidth devices such as UMA traffic or DMA transfers. Non-posted writes require a response from the receiver in the form of a "target done". Reads also cause the receiver to generate a read response.

HyperTransport also greatly facilitates power management as it is ACPI compliant. This means that changes processor sleep states (C states) can signal changes in device states (D states), e.g. powering off disks when the CPU goes to sleep.

Electrically, HyperTransport/LDT is similar to Low Voltage Differential Signaling (LVDS) operating at 2.5V.

There has been marketing confusion between the use of HT referring to HyperTransport and the use of HT to refer to Intel's Hyper-Threading feature of their Pentium 4 based microprocessors. Hyper-Threading is known as Hyper-Threading Technology (HTT) or HT-Technology. Because of this potential for confusion, the HyperTransport Consortium always uses the written out form: "HyperTransport".
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So is one of the AMD HT weaknesses is that the frequency of the CPU cannot scale higher than that of Intel's CPU? Because I read articles about overclocking an AMD cpu and it cannot hit as high as an Intel CPU.
 
i have read about hyper transport ,here or there but i still dont get it?
is it like AMD's version of Hyper Thrediing?
thanks
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The BM reponse is one of the few times you will get a link, oddly it came with no explanation.

Hypertransport is a bussing protocol for transfering data from one bus agent (the CPU) to another (the chipset). People often confuse HT for AMD for hyperthreading, when it fact it is not.

Hpertransport was developed by AMD through a consortium, it is a variant on the EV7 bus system and has the advantage that it is a serial connection and can scale to higher speeds than Intel's FSB parallel bus system.

AMD has a proprietary variant on hypertranport called coherent hypertransport. On the desktop computer it is meaningless today, but the new 4x4 platform will take advantage of it. The cHT (coherent hypertransport) is used to link CPUs directly to one another, very useful in the 2 socket and 4 socket server space. Since each processor also addresses it's own memory, then the total system memory has to be accessed through the cHT nodes. For example, if processor A needs data that resides physically in memory that is connected to processor B, then the data must be pulled by processor B and sent to processor A via the cHT link. This arrantement is called NUMA, or non-uniform memory access.

People also confuse the Hypertransport with memory access, AMD's on die memory controller is not hypertranport, it is simply a direct connection to the memory channels (this is one reason why AMD's socket pin count is much higher than Intel's).

Jack


See? If I post a link with the most accurate info, I should have said something? Why? They can explain it better than both of us.
 
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