I can only remember a few examples from the dozens of articles I've read. Let's start with the most recent, some bigwig at VIA got in trouble for stealing network technology from his former employer. Now we can go back, VIA never had a licence for P4 chipsets, but SiS did. Therefor VIA could sell P4 chipsets at a much greater profit than SiS, this hurt the industry as well as SiS themselves. VIA stole DVD decoder tech from...who was it, ALi? VIA used extortion to prevent Abit, Asus, and MSI from releasing their 735 chipset boards, when VIA's own KT266A was delayed and the KT266 couldn't compete (even in performance).
Like I said, my memory isn't perfect, so you'll have to look up other examples yourself.
As for AMD's not using Dual Channel as well as P4's, the answer is obvious: The CPU has a SINGLE DDR 64-bit channel, giving it a 128-bit DDR channel (64-bit dual-channel) makes little sense because the CPU bus has only half the bandwidth.
Whatever rediculous patent you're refering too, it doesn't matter because the math tells me that 64-bit DDR bus CPU's won't make good use of 128-bit DDR memory busses at the same frequency. 2 does not go into 1. As far as I know having the memory controller on the CPU increases performance by reducing latency between the CPU and memory controller.
<font color=blue>Only a place as big as the internet could be home to a hero as big as Crashman!</font color=blue>
<font color=red>Only a place as big as the internet could be home to an ego as large as Crashman's!</font color=red>
Like I said, my memory isn't perfect, so you'll have to look up other examples yourself.
As for AMD's not using Dual Channel as well as P4's, the answer is obvious: The CPU has a SINGLE DDR 64-bit channel, giving it a 128-bit DDR channel (64-bit dual-channel) makes little sense because the CPU bus has only half the bandwidth.
Whatever rediculous patent you're refering too, it doesn't matter because the math tells me that 64-bit DDR bus CPU's won't make good use of 128-bit DDR memory busses at the same frequency. 2 does not go into 1. As far as I know having the memory controller on the CPU increases performance by reducing latency between the CPU and memory controller.
<font color=blue>Only a place as big as the internet could be home to a hero as big as Crashman!</font color=blue>
<font color=red>Only a place as big as the internet could be home to an ego as large as Crashman's!</font color=red>